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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+sve-b16b16 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector lane index5 6bfmla z0.h, z0.h, z0.h[8]7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].8// CHECK-NEXT: bfmla z0.h, z0.h, z0.h[8]9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11bfmla z0.h, z0.h, z0.h[-1]12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].13// CHECK-NEXT: bfmla z0.h, z0.h, z0.h[-1]14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16bfmla z0.h, z0.h, z8.h[2]17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h18// CHECK-NEXT: bfmla z0.h, z0.h, z8.h[2]19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21// --------------------------------------------------------------------------//22// Invalid vector suffix23 24bfmla z0.h, z0.s, z0.s[0]25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width26// CHECK-NEXT: bfmla z0.h, z0.s, z0.s[0]27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28 29bfmla z23.s, z23.h, z13.h30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width31// CHECK-NEXT: bfmla z23.s, z23.h, z13.h32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:33 34// --------------------------------------------------------------------------//35// Invalid use of movprfx36 37movprfx z23.h, p1/m, z31.h38bfmla z23.h, z12.h, z0.h[0]39// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx40// CHECK-NEXT: bfmla z23.h, z12.h, z0.h[0]41// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:42