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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid predicate register5 6fmaxqv v0.2d, p11, z0.d7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)8// CHECK-NEXT: fmaxqv v0.2d, p11, z0.d9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11// --------------------------------------------------------------------------//12// Invalid vector register13 14fmaxqv v0.4h, p1, z0.h15// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction16// CHECK-NEXT: fmaxqv v0.4h, p1, z0.h17// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:18 19fmaxqv z1.s, p1, z0.s20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction21// CHECK-NEXT: fmaxqv z1.s, p1, z0.s22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:23 24// --------------------------------------------------------------------------//25// Invalid vector suffix26 27fmaxqv v0.2d, p1, z0.s28// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width29// CHECK-NEXT: fmaxqv v0.2d, p1, z0.s30// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:31