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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid predicate register5 6ld1q {z0.q}, p8/z, [z0.d, x0]7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)8// CHECK-NEXT: ld1q {z0.q}, p8/z, [z0.d, x0]9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11ld1q {z23.q}, p2/m, [z3.d]12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction13// CHECK-NEXT: ld1q {z23.q}, p2/m, [z3.d]14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16ld1q {z21.q}, p2.q, [z5.d]17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)18// CHECK-NEXT: ld1q {z21.q}, p2.q, [z5.d]19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21// --------------------------------------------------------------------------//22// Invalid order of base & offset23 24ld1q {z0.q}, p0/z, [x0, z0.d]25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction26// CHECK-NEXT: ld1q {z0.q}, p0/z, [x0, z0.d]27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28 29// --------------------------------------------------------------------------//30// Invalid general purpose register31 32ld1q {z0.q}, p0/z, [z0.d, sp]33// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction34// CHECK-NEXT: ld1q {z0.q}, p0/z, [z0.d, sp]35// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:36 37// --------------------------------------------------------------------------//38// Invalid suffixes39 40ld1q {z0.q}, p0/z, [z2.s]41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width42// CHECK-NEXT: ld1q {z0.q}, p0/z, [z2.s]43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:44