556 lines · plain
1; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s2; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s3 4foo:5 6; The first should encode as an expression. The second should error expecting7; a register.8 ldr x3, (foo + 4)9 ldr x3, [foo + 4]10; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58]11; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm1912; CHECK-ERRORS: error: invalid operand for instruction13 14; The last argument should be flagged as an error. rdar://957600915 ld4.8b {v0, v1, v2, v3}, [x0], #3316; CHECK-ERRORS: error: invalid operand for instruction17; CHECK-ERRORS: ld4.8b {v0, v1, v2, v3}, [x0], #3318 19 20 ldr x0, [x0, #804]21 ldr w0, [x0, #802]22 ldr x0, [x0, #804]!23 ldr w0, [w0, #301]!24 ldr x0, [x0], #80425 ldr w0, [w0], #30126 27 ldp w3, w4, [x5, #11]!28 ldp x3, x4, [x5, #12]!29 ldp q3, q4, [x5, #12]!30 ldp w3, w4, [x5], #1131 ldp x3, x4, [x5], #1232 ldp q3, q4, [x5], #1233 34 ldur x0, [x1, #-257]35 36; CHECK-ERRORS: error: index must be an integer in range [-256, 255].37; CHECK-ERRORS: ldr x0, [x0, #804]38; CHECK-ERRORS: ^39; CHECK-ERRORS: error: index must be an integer in range [-256, 255].40; CHECK-ERRORS: ldr w0, [x0, #802]41; CHECK-ERRORS: ^42; CHECK-ERRORS: error: index must be an integer in range [-256, 255].43; CHECK-ERRORS: ldr x0, [x0, #804]!44; CHECK-ERRORS: ^45; CHECK-ERRORS: error: invalid operand for instruction46; CHECK-ERRORS: ldr w0, [w0, #301]!47; CHECK-ERRORS: ^48; CHECK-ERRORS: error: index must be an integer in range [-256, 255].49; CHECK-ERRORS: ldr x0, [x0], #80450; CHECK-ERRORS: ^51; CHECK-ERRORS: error: invalid operand for instruction52; CHECK-ERRORS: ldr w0, [w0], #30153; CHECK-ERRORS: ^54; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].55; CHECK-ERRORS: ldp w3, w4, [x5, #11]!56; CHECK-ERRORS: ^57; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].58; CHECK-ERRORS: ldp x3, x4, [x5, #12]!59; CHECK-ERRORS: ^60; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].61; CHECK-ERRORS: ldp q3, q4, [x5, #12]!62; CHECK-ERRORS: ^63; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].64; CHECK-ERRORS: ldp w3, w4, [x5], #1165; CHECK-ERRORS: ^66; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].67; CHECK-ERRORS: ldp x3, x4, [x5], #1268; CHECK-ERRORS: ^69; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].70; CHECK-ERRORS: ldp q3, q4, [x5], #1271; CHECK-ERRORS: ^72; CHECK-ERRORS: error: index must be an integer in range [-256, 255].73; CHECK-ERRORS: ldur x0, [x1, #-257]74; CHECK-ERRORS: ^75 76 77ldrb w1, [x3, w3, sxtw #4]78ldrh w1, [x3, w3, sxtw #4]79ldr w1, [x3, w3, sxtw #4]80ldr x1, [x3, w3, sxtw #4]81ldr b1, [x3, w3, sxtw #4]82ldr h1, [x3, w3, sxtw #4]83ldr s1, [x3, w3, sxtw #4]84ldr d1, [x3, w3, sxtw #4]85ldr q1, [x3, w3, sxtw #1]86 87; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #088; CHECK-ERRORS:ldrb w1, [x3, w3, sxtw #4]89; CHECK-ERRORS: ^90; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #191; CHECK-ERRORS:ldrh w1, [x3, w3, sxtw #4]92; CHECK-ERRORS: ^93; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #294; CHECK-ERRORS:ldr w1, [x3, w3, sxtw #4]95; CHECK-ERRORS: ^96; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #397; CHECK-ERRORS:ldr x1, [x3, w3, sxtw #4]98; CHECK-ERRORS: ^99; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0100; CHECK-ERRORS:ldr b1, [x3, w3, sxtw #4]101; CHECK-ERRORS: ^102; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1103; CHECK-ERRORS:ldr h1, [x3, w3, sxtw #4]104; CHECK-ERRORS: ^105; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2106; CHECK-ERRORS:ldr s1, [x3, w3, sxtw #4]107; CHECK-ERRORS: ^108; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3109; CHECK-ERRORS:ldr d1, [x3, w3, sxtw #4]110; CHECK-ERRORS: ^111; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4112; CHECK-ERRORS:ldr q1, [x3, w3, sxtw #1]113; CHECK-ERRORS: ^114 115; Check that register offset addressing modes only accept 32-bit offset116; registers when using uxtw/sxtw extends. Everything else requires a 64-bit117; register.118 str d1, [x3, w3, sxtx #3]119 ldr s1, [x3, d3, sxtx #2]120 121; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3122; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]123; CHECK-ERRORS: ^124; CHECK-ERRORS: error: index must be an integer in range [-256, 255].125; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]126; CHECK-ERRORS: ^127 128; Shift immediates range checking.129 sqrshrn b4, h9, #10130 rshrn v9.8b, v11.8h, #17131 sqrshrn v7.4h, v8.4s, #39132 uqshrn2 v4.4s, v5.2d, #67133 134; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].135; CHECK-ERRORS: sqrshrn b4, h9, #10136; CHECK-ERRORS: ^137; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].138; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17139; CHECK-ERRORS: ^140; CHECK-ERRORS: error: immediate must be an integer in range [1, 16].141; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39142; CHECK-ERRORS: ^143; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].144; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67145; CHECK-ERRORS: ^146 147 148 st1.s4 {v14, v15}, [x2], #32149; CHECK-ERRORS: error: invalid type suffix for instruction150; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32151; CHECK-ERRORS: ^152 153 154 155; Load pair instructions where Rt==Rt2 and writeback load/store instructions156; where Rt==Rn or Rt2==Rn are unpredicatable.157 ldp x1, x2, [x2], #16158 ldp x2, x2, [x2], #16159 ldp w1, w2, [x2], #16160 ldp w2, w2, [x2], #16161 ldp x1, x1, [x2]162 ldp s1, s1, [x1], #8163 ldp s1, s1, [x1, #8]!164 ldp s1, s1, [x1, #8]165 ldp d1, d1, [x1], #16166 ldp d1, d1, [x1, #16]!167 ldp d1, d1, [x1, #16]168 ldp q1, q1, [x1], #32169 ldp q1, q1, [x1, #32]!170 ldp q1, q1, [x1, #32]171 172 ldr x2, [x2], #8173 ldr x2, [x2, #8]!174 ldr w2, [x2], #8175 ldr w2, [x2, #8]!176 177 str x2, [x2], #8178 str x2, [x2, #8]!179 str w2, [x2], #8180 str w2, [x2, #8]!181 182; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination183; CHECK-ERRORS: ldp x1, x2, [x2], #16184; CHECK-ERRORS: ^185; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination186; CHECK-ERRORS: ldp x2, x2, [x2], #16187; CHECK-ERRORS: ^188; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination189; CHECK-ERRORS: ldp w1, w2, [x2], #16190; CHECK-ERRORS: ^191; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination192; CHECK-ERRORS: ldp w2, w2, [x2], #16193; CHECK-ERRORS: ^194; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt195; CHECK-ERRORS: ldp x1, x1, [x2]196; CHECK-ERRORS: ^197; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt198; CHECK-ERRORS: ldp s1, s1, [x1], #8199; CHECK-ERRORS: ^200; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt201; CHECK-ERRORS: ldp s1, s1, [x1, #8]!202; CHECK-ERRORS: ^203; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt204; CHECK-ERRORS: ldp s1, s1, [x1, #8]205; CHECK-ERRORS: ^206; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt207; CHECK-ERRORS: ldp d1, d1, [x1], #16208; CHECK-ERRORS: ^209; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt210; CHECK-ERRORS: ldp d1, d1, [x1, #16]!211; CHECK-ERRORS: ^212; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt213; CHECK-ERRORS: ldp d1, d1, [x1, #16]214; CHECK-ERRORS: ^215; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt216; CHECK-ERRORS: ldp q1, q1, [x1], #32217; CHECK-ERRORS: ^218; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt219; CHECK-ERRORS: ldp q1, q1, [x1, #32]!220; CHECK-ERRORS: ^221; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt222; CHECK-ERRORS: ldp q1, q1, [x1, #32]223; CHECK-ERRORS: ^224; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source225; CHECK-ERRORS: ldr x2, [x2], #8226; CHECK-ERRORS: ^227; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source228; CHECK-ERRORS: ldr x2, [x2, #8]!229; CHECK-ERRORS: ^230; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source231; CHECK-ERRORS: ldr w2, [x2], #8232; CHECK-ERRORS: ^233; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source234; CHECK-ERRORS: ldr w2, [x2, #8]!235; CHECK-ERRORS: ^236; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source237; CHECK-ERRORS: str x2, [x2], #8238; CHECK-ERRORS: ^239; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source240; CHECK-ERRORS: str x2, [x2, #8]!241; CHECK-ERRORS: ^242; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source243; CHECK-ERRORS: str w2, [x2], #8244; CHECK-ERRORS: ^245; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source246; CHECK-ERRORS: str w2, [x2, #8]!247; CHECK-ERRORS: ^248 249; Store exclusive instructions are unpredictable if the status register clashes250; with anything.251 stlxrb w1, w1, [x5]252 stxrb w3, w5, [x3]253 stxrh w7, w9, [x7]254 stlxrh wzr, wzr, [x13]255 stxr w9, w9, [x12]256 stlxr w22, x1, [x22]257 stxr w4, x4, [x9]258 stlxr w5, x0, [x5]259; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source260; CHECK-ERRORS: stlxrb w1, w1, [x5]261; CHECK-ERRORS: ^262; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source263; CHECK-ERRORS: stxrb w3, w5, [x3]264; CHECK-ERRORS: ^265; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source266; CHECK-ERRORS: stxrh w7, w9, [x7]267; CHECK-ERRORS: ^268; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source269; CHECK-ERRORS: stlxrh wzr, wzr, [x13]270; CHECK-ERRORS: ^271; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source272; CHECK-ERRORS: stxr w9, w9, [x12]273; CHECK-ERRORS: ^274; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source275; CHECK-ERRORS: stlxr w22, x1, [x22]276; CHECK-ERRORS: ^277; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source278; CHECK-ERRORS: stxr w4, x4, [x9]279; CHECK-ERRORS: ^280; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source281; CHECK-ERRORS: stlxr w5, x0, [x5]282; CHECK-ERRORS: ^283 284 stxp w0, w0, w1, [x3]285 stxp w0, w1, w0, [x5]286 stxp w10, w4, w5, [x10]287 stxp wzr, xzr, x4, [x5]288 stxp w3, x5, x3, [sp]289 stxp w25, x4, x2, [x25]290; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source291; CHECK-ERRORS: stxp w0, w0, w1, [x3]292; CHECK-ERRORS: ^293; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source294; CHECK-ERRORS: stxp w0, w1, w0, [x5]295; CHECK-ERRORS: ^296; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source297; CHECK-ERRORS: stxp w10, w4, w5, [x10]298; CHECK-ERRORS: ^299; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source300; CHECK-ERRORS: stxp wzr, xzr, x4, [x5]301; CHECK-ERRORS: ^302; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source303; CHECK-ERRORS: stxp w3, x5, x3, [sp]304; CHECK-ERRORS: ^305; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source306; CHECK-ERRORS: stxp w25, x4, x2, [x25]307; CHECK-ERRORS: ^308 309 310; The validity checking for shifted-immediate operands. rdar://13174476311; Where the immediate is out of range.312 add w1, w2, w3, lsr #75313 314; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]315; CHECK-ERRORS: add w1, w2, w3, lsr #75316; CHECK-ERRORS: ^317 318; logical instructions on 32-bit regs with shift > 31 is not legal319orr w0, w0, w0, lsl #32320; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]321; CHECK-ERRORS: orr w0, w0, w0, lsl #32322; CHECK-ERRORS: ^323eor w0, w0, w0, lsl #32324; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]325; CHECK-ERRORS: eor w0, w0, w0, lsl #32326; CHECK-ERRORS: ^327and w0, w0, w0, lsl #32328; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]329; CHECK-ERRORS: and w0, w0, w0, lsl #32330; CHECK-ERRORS: ^331ands w0, w0, w0, lsl #32332; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]333; CHECK-ERRORS: ands w0, w0, w0, lsl #32334; CHECK-ERRORS: ^335 336; Relocated expressions should not be accepted for 32-bit adds or sub (imm)337add w3, w5, sym@PAGEOFF338; CHECK-ERRORS: error: invalid immediate expression339; CHECK-ERRORS: add w3, w5, sym@PAGEOFF340; CHECK-ERRORS: ^341 342adds w3, w5, sym@PAGEOFF343adds x9, x12, sym@PAGEOFF344; CHECK-ERRORS: error: invalid immediate expression345; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF346; CHECK-ERRORS: ^347; CHECK-ERRORS: error: invalid immediate expression348; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF349; CHECK-ERRORS: ^350 351sub x3, x5, sym@PAGEOFF352sub w20, w30, sym@PAGEOFF353; CHECK-ERRORS: error: invalid immediate expression354; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF355; CHECK-ERRORS: ^356; CHECK-ERRORS: error: invalid immediate expression357; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF358; CHECK-ERRORS: ^359 360subs w9, w10, sym@PAGEOFF361subs x20, x30, sym@PAGEOFF362; CHECK-ERRORS: error: invalid immediate expression363; CHECK-ERRORS: subs w9, w10, sym@PAGEOFF364; CHECK-ERRORS: ^365; CHECK-ERRORS: error: invalid immediate expression366; CHECK-ERRORS: subs x20, x30, sym@PAGEOFF367; CHECK-ERRORS: ^368 369add w3, w5, sym@PAGEOFF - 3-2370; CHECK-ERRORS: [[#@LINE-1]]:28: error: unexpected token in argument list371 372tbl v0.8b, { v1 }, v0.8b373tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b374tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b375tbx v2.8b, { v0 }, v6.8b376; CHECK-ERRORS: error: invalid operand for instruction377; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b378; CHECK-ERRORS: ^379; CHECK-ERRORS: error: invalid operand for instruction380; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b381; CHECK-ERRORS: ^382; CHECK-ERRORS: error: invalid operand for instruction383; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b384; CHECK-ERRORS: ^385; CHECK-ERRORS: error: invalid operand for instruction386; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b387; CHECK-ERRORS: ^388 389b.c #0x4390; CHECK-ERRORS: error: invalid condition code391; CHECK-ERRORS: b.c #0x4392; CHECK-ERRORS: ^393 394ic ialluis, x0395; CHECK-ERRORS: error: specified ic op does not use a register396ic iallu, x0397; CHECK-ERRORS: error: specified ic op does not use a register398ic ivau399; CHECK-ERRORS: error: specified ic op requires a register400 401dc zva402; CHECK-ERRORS: error: specified dc op requires a register403dc ivac404; CHECK-ERRORS: error: specified dc op requires a register405dc isw406; CHECK-ERRORS: error: specified dc op requires a register407dc cvac408; CHECK-ERRORS: error: specified dc op requires a register409dc csw410; CHECK-ERRORS: error: specified dc op requires a register411dc cvau412; CHECK-ERRORS: error: specified dc op requires a register413dc civac414; CHECK-ERRORS: error: specified dc op requires a register415dc cisw416; CHECK-ERRORS: error: specified dc op requires a register417 418at s1e1r419; CHECK-ERRORS: error: specified at op requires a register420at s1e2r421; CHECK-ERRORS: error: specified at op requires a register422at s1e3r423; CHECK-ERRORS: error: specified at op requires a register424at s1e1w425; CHECK-ERRORS: error: specified at op requires a register426at s1e2w427; CHECK-ERRORS: error: specified at op requires a register428at s1e3w429; CHECK-ERRORS: error: specified at op requires a register430at s1e0r431; CHECK-ERRORS: error: specified at op requires a register432at s1e0w433; CHECK-ERRORS: error: specified at op requires a register434at s12e1r435; CHECK-ERRORS: error: specified at op requires a register436at s12e1w437; CHECK-ERRORS: error: specified at op requires a register438at s12e0r439; CHECK-ERRORS: error: specified at op requires a register440at s12e0w441; CHECK-ERRORS: error: specified at op requires a register442 443tlbi vmalle1is, x0444; CHECK-ERRORS: error: specified tlbi op does not use a register445tlbi vmalle1, x0446; CHECK-ERRORS: error: specified tlbi op does not use a register447tlbi alle1is, x0448; CHECK-ERRORS: error: specified tlbi op does not use a register449tlbi alle2is, x0450; CHECK-ERRORS: error: specified tlbi op does not use a register451tlbi alle3is, x0452; CHECK-ERRORS: error: specified tlbi op does not use a register453tlbi alle1, x0454; CHECK-ERRORS: error: specified tlbi op does not use a register455tlbi alle2, x0456; CHECK-ERRORS: error: specified tlbi op does not use a register457tlbi alle3, x0458; CHECK-ERRORS: error: specified tlbi op does not use a register459tlbi vae1is460; CHECK-ERRORS: error: specified tlbi op requires a register461tlbi vae2is462; CHECK-ERRORS: error: specified tlbi op requires a register463tlbi vae3is464; CHECK-ERRORS: error: specified tlbi op requires a register465tlbi aside1is466; CHECK-ERRORS: error: specified tlbi op requires a register467tlbi vaae1is468; CHECK-ERRORS: error: specified tlbi op requires a register469tlbi vale1is470; CHECK-ERRORS: error: specified tlbi op requires a register471tlbi vaale1is472; CHECK-ERRORS: error: specified tlbi op requires a register473tlbi vale2is474; CHECK-ERRORS: error: specified tlbi op requires a register475tlbi vale3is476; CHECK-ERRORS: error: specified tlbi op requires a register477tlbi vae1478; CHECK-ERRORS: error: specified tlbi op requires a register479tlbi vae2480; CHECK-ERRORS: error: specified tlbi op requires a register481tlbi vae3482; CHECK-ERRORS: error: specified tlbi op requires a register483tlbi aside1484; CHECK-ERRORS: error: specified tlbi op requires a register485tlbi vaae1486; CHECK-ERRORS: error: specified tlbi op requires a register487tlbi vale1488; CHECK-ERRORS: error: specified tlbi op requires a register489tlbi vale2490; CHECK-ERRORS: error: specified tlbi op requires a register491tlbi vale3492; CHECK-ERRORS: error: specified tlbi op requires a register493 494 495; Check that we give the proper "too few operands" diagnostic even when496; using short-form NEON.497 498 add.16b v0, v1, v2, v3499 add.8b v0, v1500 sub.8h v0, v1501 fadd.4s v0502 fmul.2s503 504; CHECK-ERRORS: error: invalid operand for instruction505; CHECK-ERRORS: add.16b v0, v1, v2, v3506; CHECK-ERRORS: ^507; CHECK-ERRORS: error: too few operands for instruction508; CHECK-ERRORS: add.8b v0, v1509; CHECK-ERRORS: ^510; CHECK-ERRORS: error: too few operands for instruction511; CHECK-ERRORS: sub.8h v0, v1512; CHECK-ERRORS: ^513; CHECK-ERRORS: error: too few operands for instruction514; CHECK-ERRORS: fadd.4s v0515; CHECK-ERRORS: ^516; CHECK-ERRORS: error: too few operands for instruction517; CHECK-ERRORS: fmul.2s518; CHECK-ERRORS: ^519 520; Also for 2-operand instructions.521 522 frsqrte.4s v0, v1, v2523 frsqrte.2s v0524 frecpe.2d525 526; CHECK-ERRORS: error: invalid operand for instruction527; CHECK-ERRORS: frsqrte.4s v0, v1, v2528; CHECK-ERRORS: ^529; CHECK-ERRORS: error: too few operands for instruction530; CHECK-ERRORS: frsqrte.2s v0531; CHECK-ERRORS: ^532; CHECK-ERRORS: error: too few operands for instruction533; CHECK-ERRORS: frecpe.2d534; CHECK-ERRORS: ^535 536; And check that we do the same for non-NEON instructions.537 538 b.ne539 b.eq 0, 0540 541; CHECK-ERRORS: error: too few operands for instruction542; CHECK-ERRORS: b.ne543; CHECK-ERRORS: ^544; CHECK-ERRORS: error: invalid operand for instruction545; CHECK-ERRORS: b.eq 0, 0546; CHECK-ERRORS: ^547 548; Check that we give the proper "too few operands" diagnostic instead of549; asserting.550 551 ldr552 553; CHECK-ERRORS: error: too few operands for instruction554; CHECK-ERRORS: ldr555; CHECK-ERRORS: ^556