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1// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+i8mm < %s 2>&1 | FileCheck %s2 3// No interesting edge cases for [US]MMLA, except for the fact that the data4// types are fixed (no 64-bit version), and USMMLA exists, but SUMMLA does not.5smmla v1.2s, v16.8b, v31.8b6// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction7summla v1.4s, v16.16b, v31.16b8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unrecognized instruction mnemonic, did you mean: smmla, ummla, usmmla?9 10// USDOT (vector) has two valid data type combinations, others are rejected.11usdot v3.4s, v15.8b, v30.8b12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction13usdot v3.2s, v15.16b, v30.16b14// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction15 16// For USDOT and SUDOT (indexed), the index is in range [0,3] (regardless of data types)17usdot v31.2s, v1.8b, v2.4b[4]18// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].19usdot v31.4s, v1.16b, v2.4b[4]20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].21sudot v31.2s, v1.8b, v2.4b[4]22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].23sudot v31.4s, v1.16b, v2.4b[4]24// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].25 26// The arrangement specifiers of the first two operands must match.27usdot v31.4s, v1.8b, v2.4b[0]28// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction29usdot v31.2s, v1.16b, v2.4b[0]30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction31sudot v31.4s, v1.8b, v2.4b[0]32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction33sudot v31.2s, v1.16b, v2.4b[0]34// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction35