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1// RUN: llvm-mc -triple=arm64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s2// RUN: not llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO-ARM64 %s3 4// Check that the assembler can handle the documented syntax for AArch645 6//------------------------------------------------------------------------------7// Instructions for crypto8//------------------------------------------------------------------------------9 10 aese v0.16b, v1.16b11 aesd v0.16b, v1.16b12 aesmc v0.16b, v1.16b13 aesimc v0.16b, v1.16b14 15// CHECK-NO-CRYPTO: error: instruction requires a CPU feature not currently enabled16// CHECK-NO-CRYPTO-ARM64: error: instruction requires: aes17// CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e]18// CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e]19// CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e]20// CHECK: aesimc v0.16b, v1.16b // encoding: [0x20,0x78,0x28,0x4e]21 22 sha1h s0, s123 sha1su1 v0.4s, v1.4s24 sha256su0 v0.4s, v1.4s25 26// CHECK: sha1h s0, s1 // encoding: [0x20,0x08,0x28,0x5e]27// CHECK: sha1su1 v0.4s, v1.4s // encoding: [0x20,0x18,0x28,0x5e]28// CHECK: sha256su0 v0.4s, v1.4s // encoding: [0x20,0x28,0x28,0x5e]29 30 sha1c q0, s1, v2.4s31 sha1p q0, s1, v2.4s32 sha1m q0, s1, v2.4s33 sha1su0 v0.4s, v1.4s, v2.4s34 sha256h q0, q1, v2.4s35 sha256h2 q0, q1, v2.4s36 sha256su1 v0.4s, v1.4s, v2.4s37 38// CHECK: sha1c q0, s1, v2.4s // encoding: [0x20,0x00,0x02,0x5e]39// CHECK: sha1p q0, s1, v2.4s // encoding: [0x20,0x10,0x02,0x5e]40// CHECK: sha1m q0, s1, v2.4s // encoding: [0x20,0x20,0x02,0x5e]41// CHECK: sha1su0 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x30,0x02,0x5e]42// CHECK: sha256h q0, q1, v2.4s // encoding: [0x20,0x40,0x02,0x5e]43// CHECK: sha256h2 q0, q1, v2.4s // encoding: [0x20,0x50,0x02,0x5e]44// CHECK: sha256su1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x60,0x02,0x5e]45