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1// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s2 3// Check that the assembler can handle the documented syntax for AArch644 5//------------------------------------------------------------------------------6// Instructions across vector registers7//------------------------------------------------------------------------------8 9 tbl v0.8b, { v1.16b }, v2.8b10 tbl v0.8b, { v1.16b, v2.16b }, v2.8b11 tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b12 tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b13 tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b14 15// CHECK: tbl v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x00,0x02,0x0e]16// CHECK: tbl v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x20,0x02,0x0e]17// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x40,0x02,0x0e]18// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x60,0x02,0x0e]19// CHECK: tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x63,0x02,0x0e]20 21 tbl v0.16b, { v1.16b }, v2.16b22 tbl v0.16b, { v1.16b, v2.16b }, v2.16b23 tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b24 tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b25 tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b26 27// CHECK: tbl v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x00,0x02,0x4e]28// CHECK: tbl v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x20,0x02,0x4e]29// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x40,0x02,0x4e]30// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x60,0x02,0x4e]31// CHECK: tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x63,0x02,0x4e]32 33 tbx v0.8b, { v1.16b }, v2.8b34 tbx v0.8b, { v1.16b, v2.16b }, v2.8b35 tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b36 tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b37 tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b38 39// CHECK: tbx v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x10,0x02,0x0e]40// CHECK: tbx v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x30,0x02,0x0e]41// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x50,0x02,0x0e]42// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x70,0x02,0x0e]43// CHECK: tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x73,0x02,0x0e]44 45 tbx v0.16b, { v1.16b }, v2.16b46 tbx v0.16b, { v1.16b, v2.16b }, v2.16b47 tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b48 tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b49 tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b50 51// CHECK: tbx v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x10,0x02,0x4e]52// CHECK: tbx v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x30,0x02,0x4e]53// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x50,0x02,0x4e]54// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x70,0x02,0x4e]55// CHECK: tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x73,0x02,0x4e]56