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1// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI2// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:3 4//===----------------------------------------------------------------------===//5// Floating-point expressions are not supported6//===----------------------------------------------------------------------===//7 8s_sub_u32 s0, s0, -1.0 + 100000000009// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction10 11t=1000000000012s_sub_u32 s0, s0, 1.0 + t13// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction14 15v_ceil_f32 v1, 1.0 + 1.016// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction17 18v_ceil_f32 v1, -1.0 + 1.019// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction20 21//===----------------------------------------------------------------------===//22// Constant expressions may be used with SP3 'abs' modifiers |...|23// These expressions must be primary expressions to avoid incorrect24// interpretation of closing "|".25//===----------------------------------------------------------------------===//26 27i1=128fm1=0xBF800000 // -1.0f29hm1=0xBC00 // -1.0h30 31v_ceil_f32 v1, |i1|32// VI: v_ceil_f32_e32 v1, 1 ; encoding: [0x81,0x3a,0x02,0x7e]33 34v_ceil_f32 v1, |(i1+1)|35// VI: v_ceil_f32_e32 v1, 2 ; encoding: [0x82,0x3a,0x02,0x7e]36 37v_ceil_f32 v1, |-(i1+1)|38// VI: v_ceil_f32_e32 v1, 0x7ffffffe ; encoding: [0xff,0x3a,0x02,0x7e,0xfe,0xff,0xff,0x7f]39 40v_ceil_f32 v1, |fm1|41// VI: v_ceil_f32_e32 v1, 1.0 ; encoding: [0xf2,0x3a,0x02,0x7e]42 43v_mad_f16 v5, v1, v2, |i1|44// VI: v_mad_f16 v5, v1, v2, |1| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0x06,0x02]45 46v_mad_f16 v5, v1, v2, |(i1+1)|47// VI: v_mad_f16 v5, v1, v2, |2| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0a,0x02]48 49v_mad_f16 v5, v1, v2, |hm1|50// VI: v_mad_f16 v5, v1, v2, |-1.0| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0xce,0x03]51 52// Only primary expressions are allowed53 54v_ceil_f32 v1, |1+i1|55// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: expected vertical bar56 57v_ceil_f32 v1, |i1+1|58// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: expected vertical bar59 60//===----------------------------------------------------------------------===//61// Constant expressions may be used with 'abs' and 'neg' modifiers.62//===----------------------------------------------------------------------===//63 64v_ceil_f32 v1, abs(i1)65// VI: v_ceil_f32_e32 v1, 1 ; encoding: [0x81,0x3a,0x02,0x7e]66 67v_ceil_f32 v1, abs(i1+1)68// VI: v_ceil_f32_e32 v1, 2 ; encoding: [0x82,0x3a,0x02,0x7e]69 70v_ceil_f32 v1, abs(-(i1+1))71// VI: v_ceil_f32_e32 v1, 0x7ffffffe ; encoding: [0xff,0x3a,0x02,0x7e,0xfe,0xff,0xff,0x7f]72 73v_ceil_f32 v1, abs(fm1)74// VI: v_ceil_f32_e32 v1, 1.0 ; encoding: [0xf2,0x3a,0x02,0x7e]75 76v_mad_f16 v5, v1, v2, abs(i1)77// VI: v_mad_f16 v5, v1, v2, |1| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0x06,0x02]78 79v_mad_f16 v5, v1, v2, abs(i1+1)80// VI: v_mad_f16 v5, v1, v2, |2| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0a,0x02]81 82v_mad_f16 v5, v1, v2, abs(hm1)83// VI: v_mad_f16 v5, v1, v2, |-1.0| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0xce,0x03]84 85v_ceil_f32 v1, neg(i1+1)86// VI: v_ceil_f32_e32 v1, 0x80000002 ; encoding: [0xff,0x3a,0x02,0x7e,0x02,0x00,0x00,0x80]87 88v_ceil_f32 v1, neg(1+i1)89// VI: v_ceil_f32_e32 v1, 0x80000002 ; encoding: [0xff,0x3a,0x02,0x7e,0x02,0x00,0x00,0x80]90 91v_ceil_f32 v1, neg(-i1+3)92// VI: v_ceil_f32_e32 v1, 0x80000002 ; encoding: [0xff,0x3a,0x02,0x7e,0x02,0x00,0x00,0x80]93 94v_ceil_f32 v1, neg(-(i1+1))95// VI: v_ceil_f32_e32 v1, 0x7ffffffe ; encoding: [0xff,0x3a,0x02,0x7e,0xfe,0xff,0xff,0x7f]96 97v_ceil_f32 v1, neg(fm1)98// VI: v_ceil_f32_e32 v1, 1.0 ; encoding: [0xf2,0x3a,0x02,0x7e]99 100v_mad_f16 v5, v1, v2, neg(hm1)101// VI: v_mad_f16 v5, v1, v2, neg(-1.0) ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xce,0x83]102 103//===----------------------------------------------------------------------===//104// Constant expressions may be used where inline constants are accepted.105//===----------------------------------------------------------------------===//106 107v_ceil_f64 v[0:1], i1+1108// VI: v_ceil_f64_e32 v[0:1], 2 ; encoding: [0x82,0x30,0x00,0x7e]109 110v_and_b32 v0, i1+1, v0111// VI: v_and_b32_e32 v0, 2, v0 ; encoding: [0x82,0x00,0x00,0x26]112 113v_and_b32 v0, 1+i1, v0114// VI: v_and_b32_e32 v0, 2, v0 ; encoding: [0x82,0x00,0x00,0x26]115 116v_and_b32 v0, -i1+3, v0117// VI: v_and_b32_e32 v0, 2, v0 ; encoding: [0x82,0x00,0x00,0x26]118 119v_and_b32 v0, -(i1+1), v0120// VI: v_and_b32_e32 v0, -2, v0 ; encoding: [0xc2,0x00,0x00,0x26]121 122v_add_u16 v0, (i1+4)/2, v1123// VI: v_add_u16_e32 v0, 2, v1 ; encoding: [0x82,0x02,0x00,0x4c]124 125buffer_atomic_inc v1, off, s[8:11], i1+1 glc126// VI: buffer_atomic_inc v1, off, s[8:11], 2 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x02,0x82]127 128s_addk_i32 s2, i1+1129// VI: s_addk_i32 s2, 0x2 ; encoding: [0x02,0x00,0x02,0xb7]130 131s_cmpk_eq_i32 s2, i1+1132// VI: s_cmpk_eq_i32 s2, 0x2 ; encoding: [0x02,0x00,0x02,0xb1]133 134s_setreg_imm32_b32 0x6, i1+1135// VI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 2 ; encoding: [0x06,0x00,0x00,0xba,0x02,0x00,0x00,0x00]136 137v_madak_f16 v1, v2, v3, i1+1138// VI: v_madak_f16 v1, v2, v3, 0x2 ; encoding: [0x02,0x07,0x02,0x4a,0x02,0x00,0x00,0x00]139 140s_set_gpr_idx_on s0, i1+1141// VI: s_set_gpr_idx_on s0, gpr_idx(SRC1) ; encoding: [0x00,0x02,0x11,0xbf]142 143s_atc_probe i1-1, s[4:5], i1+1144// VI: s_atc_probe 0, s[4:5], 0x2 ; encoding: [0x02,0x00,0x9a,0xc0,0x02,0x00,0x00,0x00]145 146s_load_dword s1, s[2:3], i1+1 glc147// VI: s_load_dword s1, s[2:3], 0x2 glc ; encoding: [0x41,0x00,0x03,0xc0,0x02,0x00,0x00,0x00]148 149//===----------------------------------------------------------------------===//150// Constant expressions may be used where literals are accepted.151//===----------------------------------------------------------------------===//152 153v_ceil_f64 v[0:1], i1+100154// VI: v_ceil_f64_e32 v[0:1], 0x65 ; encoding: [0xff,0x30,0x00,0x7e,0x65,0x00,0x00,0x00]155 156v_and_b32 v0, i1+100, v0157// VI: v_and_b32_e32 v0, 0x65, v0 ; encoding: [0xff,0x00,0x00,0x26,0x65,0x00,0x00,0x00]158 159v_and_b32 v0, -i1+102, v0160// VI: v_and_b32_e32 v0, 0x65, v0 ; encoding: [0xff,0x00,0x00,0x26,0x65,0x00,0x00,0x00]161 162v_add_u16 v0, (i1+100)*2, v0163// VI: v_add_u16_e32 v0, 0xca, v0 ; encoding: [0xff,0x00,0x00,0x4c,0xca,0x00,0x00,0x00]164 165//===----------------------------------------------------------------------===//166// Constant expressions may be used with Name:Value modifiers.167//===----------------------------------------------------------------------===//168 169buffer_load_dword v1, off, s[4:7], s1 offset:-1+1170// VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]171 172buffer_load_dword v1, off, s[4:7], s1 offset:i1+4173// VI: buffer_load_dword v1, off, s[4:7], s1 offset:5 ; encoding: [0x05,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]174 175buffer_load_dword v1, off, s[4:7], s1 offset:4+i1176// VI: buffer_load_dword v1, off, s[4:7], s1 offset:5 ; encoding: [0x05,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]177 178buffer_load_dword v1, off, s[4:7], s1 offset:-i1+4179// VI: buffer_load_dword v1, off, s[4:7], s1 offset:3 ; encoding: [0x03,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]180 181//===----------------------------------------------------------------------===//182// Relocatable expressions can be used with 32-bit instructions.183//===----------------------------------------------------------------------===//184 185v_ceil_f32 v1, -u186// VI: v_ceil_f32_e32 v1, -u ; encoding: [0xff,0x3a,0x02,0x7e,A,A,A,A]187// VI-NEXT: ; fixup A - offset: 4, value: -u, kind: FK_PCRel_4188 189v_and_b32 v0, u+1, v0190// VI: v_and_b32_e32 v0, u+1, v0 ; encoding: [0xff,0x00,0x00,0x26,A,A,A,A]191// VI-NEXT: ; fixup A - offset: 4, value: u+1, kind: FK_PCRel_4192 193//===----------------------------------------------------------------------===//194// Relocatable expressions cannot be used as 16/20/21/64-bit operands.195//===----------------------------------------------------------------------===//196 197v_ceil_f64 v[0:1], u198// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction199 200v_add_u16 v0, u, v0201// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction202 203s_addk_i32 s2, u204// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction205 206s_load_dword s1, s[2:3], u glc207// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction208 209//===----------------------------------------------------------------------===//210// Relocatable expressions cannot be used with VOP3 modifiers.211//===----------------------------------------------------------------------===//212 213v_ceil_f32 v1, |u|214// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression215 216v_ceil_f32 v1, neg(u)217// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression218 219v_ceil_f32 v1, abs(u)220// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression221 222//===----------------------------------------------------------------------===//223// Misc tests with symbols.224//===----------------------------------------------------------------------===//225 226.globl global227.globl gds228 229// Parse a global expression230s_mov_b32 s0, global231// VI: s_mov_b32 s0, global ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]232// VI-NEXT: ; fixup A - offset: 4, value: global, kind: FK_PCRel_4233 234// Use a token with the same name as a global235ds_gws_init v2 gds236// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x02,0x00,0x00,0x00]237 238// Use a global with the same name as a token239s_mov_b32 s0, gds240// VI: s_mov_b32 s0, gds ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]241// VI-NEXT: ; fixup A - offset: 4, value: gds, kind: FK_PCRel_4242 243// Use a binary expression244s_mov_b32 s0, gds+4245// VI: s_mov_b32 s0, gds+4 ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]246// VI-NEXT: ; fixup A - offset: 4, value: gds+4, kind: FK_PCRel_4247 248// Consecutive instructions with no blank line in between to make sure we249// don't call Lex() too many times.250s_add_u32 s0, s0, global+4251s_addc_u32 s1, s1, 0252// VI: s_add_u32 s0, s0, global+4253// VI: s_addc_u32 s1, s1, 0254 255// Use a computed expression that results in an inline immediate.256.set foo, 4257s_mov_b32 s0, foo+2258// VI: s_mov_b32 s0, 6 ; encoding: [0x86,0x00,0x80,0xbe]259 260// Use a computed expression that results in a non-inline immediate.261.set foo, 512262s_mov_b32 s0, foo+2263// VI: s_mov_b32 s0, 0x202 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00]264 265v_mul_f32 v0, foo+2, v2266// VI: v_mul_f32_e32 v0, 0x202, v2 ; encoding: [0xff,0x04,0x00,0x0a,0x02,0x02,0x00,0x00]267 268BB1:269v_nop_e64270BB2:271s_sub_u32 vcc_lo, vcc_lo, (BB2+4)-BB1272// VI: s_sub_u32 vcc_lo, vcc_lo, BB2+4-BB1 ; encoding: [0x6a,0xff,0xea,0x80,A,A,A,A]273// VI-NEXT: ; fixup A - offset: 4, value: BB2+4-BB1, kind: FK_Data_4274s_add_u32 vcc_lo, vcc_lo, (BB2-BB1)&4294967295275// VI: s_add_u32 vcc_lo, vcc_lo, (BB2-BB1)&4294967295 ; encoding: [0x6a,0xff,0x6a,0x80,A,A,A,A]276// VI-NEXT: ; fixup A - offset: 4, value: (BB2-BB1)&4294967295, kind: FK_Data_4277s_addc_u32 vcc_hi, vcc_hi, (BB2-BB1)>>32278// VI: s_addc_u32 vcc_hi, vcc_hi, (BB2-BB1)>>32 ; encoding: [0x6b,0xff,0x6b,0x82,A,A,A,A]279// VI-NEXT: ; fixup A - offset: 4, value: (BB2-BB1)>>32, kind: FK_Data_4280 281t=1282s_sub_u32 s0, s0, -t283// VI: s_sub_u32 s0, s0, -1 ; encoding: [0x00,0xc1,0x80,0x80]284 285t=-1286s_sub_u32 s0, s0, -t287// VI: s_sub_u32 s0, s0, 1 ; encoding: [0x00,0x81,0x80,0x80]288 289s_sub_u32 s0, s0, -2+1290// VI: s_sub_u32 s0, s0, -1 ; encoding: [0x00,0xc1,0x80,0x80]291 292t=1293s_sub_u32 s0, s0, -2+t294// VI: s_sub_u32 s0, s0, -1 ; encoding: [0x00,0xc1,0x80,0x80]295 296//===----------------------------------------------------------------------===//297// Symbols may look like registers.298// They should be allowed in expressions if there is no ambiguity.299//===----------------------------------------------------------------------===//300 301v=1302v_sin_f32 v0, -v303// VI: v_sin_f32_e32 v0, -1 ; encoding: [0xc1,0x52,0x00,0x7e]304 305s=1306s_not_b32 s0, -s307// VI: s_not_b32 s0, -1 ; encoding: [0xc1,0x04,0x80,0xbe]308 309ttmp=1310s_not_b32 s0, -ttmp311// VI: s_not_b32 s0, -1 ; encoding: [0xc1,0x04,0x80,0xbe]312 313//===----------------------------------------------------------------------===//314// Registers have priority over symbols.315//===----------------------------------------------------------------------===//316 317v=1318v_sin_f32 v0, -v[0]319// VI: v_sin_f32_e64 v0, -v0 ; encoding: [0x00,0x00,0x69,0xd1,0x00,0x01,0x00,0x20]320 321s0=1322v_sin_f32 v0, -s0323// VI: v_sin_f32_e64 v0, -s0 ; encoding: [0x00,0x00,0x69,0xd1,0x00,0x00,0x00,0x20]324 325ttmp0=1326v_sin_f32 v0, -[ttmp0]327// VI: v_sin_f32_e64 v0, -ttmp0 ; encoding: [0x00,0x00,0x69,0xd1,0x70,0x00,0x00,0x20]328 329//===----------------------------------------------------------------------===//330// Incorrect register names and unsupported registers should not be interpreted331// as expressions, rather they should trigger errors.332//===----------------------------------------------------------------------===//333 334s1000=1335v_sin_f32 v0, -s1000336// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range337 338xnack_mask_lo=1339v_sin_f32 v0, xnack_mask_lo340// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: xnack_mask_lo register not available on this GPU341