1380 lines · plain
1// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace2 3//==============================================================================4// operands are not valid for this GPU or mode5 6image_atomic_add v252, v2, s[8:15]7// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing dim operand8// CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15]9// CHECK-NEXT:{{^}}^10 11//==============================================================================12// duplicate data format13 14tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]15// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate data format16// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]17// CHECK-NEXT:{{^}} ^18 19//==============================================================================20// duplicate numeric format21 22tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT]23// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate numeric format24// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT]25// CHECK-NEXT:{{^}} ^26 27//==============================================================================28// expected ')' in parentheses expression29 30v_bfe_u32 v0, 1+(100, v1, v231// CHECK: :[[#@LINE-1]]:21: error: expected ')'32// CHECK-NEXT:{{^}}v_bfe_u32 v0, 1+(100, v1, v233// CHECK-NEXT:{{^}} ^34 35//==============================================================================36// expected a 12-bit signed offset37 38global_load_dword v1, v[3:4] off, offset:-409739// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 12-bit signed offset40// CHECK-NEXT:{{^}}global_load_dword v1, v[3:4] off, offset:-409741// CHECK-NEXT:{{^}} ^42 43scratch_load_dword v0, v1, off offset:-2049 glc slc44// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 12-bit signed offset45// CHECK-NEXT:{{^}}scratch_load_dword v0, v1, off offset:-2049 glc slc46// CHECK-NEXT:{{^}} ^47 48//==============================================================================49// expected a 16-bit signed jump offset50 51s_branch 0x1000052// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 16-bit signed jump offset53// CHECK-NEXT:{{^}}s_branch 0x1000054// CHECK-NEXT:{{^}} ^55 56//==============================================================================57// expected a 2-bit lane id58 59ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)60// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit lane id61// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)62// CHECK-NEXT:{{^}} ^63 64//==============================================================================65// expected a 20-bit unsigned offset66 67s_atc_probe_buffer 0x1, s[8:11], -168// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset69// CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], -170// CHECK-NEXT:{{^}} ^71 72s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF0000073// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset74// CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF0000075// CHECK-NEXT:{{^}} ^76 77s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF78// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset79// CHECK-NEXT:{{^}}s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF80// CHECK-NEXT:{{^}} ^81 82//==============================================================================83// expected a 21-bit signed offset84 85s_atc_probe 0x7, s[4:5], 0x1FFFFF86// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 21-bit signed offset87// CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], 0x1FFFFF88// CHECK-NEXT:{{^}} ^89 90s_atomic_swap s5, s[2:3], 0x1FFFFF91// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 21-bit signed offset92// CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF93// CHECK-NEXT:{{^}} ^94 95//==============================================================================96// expected a 2-bit value97 98v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x099// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit value100// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0101// CHECK-NEXT:{{^}} ^102 103v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0104// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit value105// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0106// CHECK-NEXT:{{^}} ^107 108//==============================================================================109// expected a 3-bit value110 111v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]112// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 3-bit value113// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]114// CHECK-NEXT:{{^}} ^115 116v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]117// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 3-bit value118// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]119// CHECK-NEXT:{{^}} ^120 121//==============================================================================122// expected a 5-character mask123 124ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")125// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 5-character mask126// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")127// CHECK-NEXT:{{^}} ^128 129//==============================================================================130// expected a closing parentheses131 132ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3133// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses134// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3135// CHECK-NEXT:{{^}} ^136 137ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)138// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses139// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)140// CHECK-NEXT:{{^}} ^141 142//==============================================================================143// expected a closing parenthesis144 145s_sendmsg sendmsg(2, 2, 0, 0)146// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parenthesis147// CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 0, 0)148// CHECK-NEXT:{{^}} ^149 150s_waitcnt vmcnt(0151// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parenthesis152// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0153// CHECK-NEXT:{{^}} ^154 155//==============================================================================156// expected a closing square bracket157 158s_mov_b32 s1, s[0 1159// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket160// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 1161// CHECK-NEXT:{{^}} ^162 163s_mov_b32 s1, s[0 s0164// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket165// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 s0166// CHECK-NEXT:{{^}} ^167 168tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8]169// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket170// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8]171// CHECK-NEXT:{{^}} ^172 173tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT174// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket175// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT176// CHECK-NEXT:{{^}} ^177 178v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1179// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket180// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1181// CHECK-NEXT:{{^}} ^182 183v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1,184// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket185// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1,186// CHECK-NEXT:{{^}} ^187 188v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[189// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket190// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[191// CHECK-NEXT:{{^}} ^192 193v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]194// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket195// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]196// CHECK-NEXT:{{^}} ^197 198v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)199// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket200// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)201// CHECK-NEXT:{{^}} ^202 203v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0204// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket205// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0206// CHECK-NEXT:{{^}} ^207 208//==============================================================================209// expected a colon210 211ds_swizzle_b32 v8, v2 offset212// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a colon213// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset214// CHECK-NEXT:{{^}} ^215 216ds_swizzle_b32 v8, v2 offset-217// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a colon218// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset-219// CHECK-NEXT:{{^}} ^220 221//==============================================================================222// expected a comma223 224ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM225// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma226// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM227// CHECK-NEXT:{{^}} ^228 229ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)230// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma231// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)232// CHECK-NEXT:{{^}} ^233 234s_setreg_b32 hwreg(1,2 3), s2235// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma236// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(1,2 3), s2237// CHECK-NEXT:{{^}} ^238 239v_pk_add_u16 v1, v2, v3 op_sel:[0 0]240// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma241// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0]242// CHECK-NEXT:{{^}} ^243 244v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]245// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma246// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]247// CHECK-NEXT:{{^}} ^248 249v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0250// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma251// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0252// CHECK-NEXT:{{^}} ^253 254//==============================================================================255// expected a comma or a closing parenthesis256 257s_setreg_b32 hwreg(1 2,3), s2258// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing parenthesis259// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(1 2,3), s2260// CHECK-NEXT:{{^}} ^261 262//==============================================================================263// expected a comma or a closing square bracket264 265s_mov_b64 s[10:11], [s0266// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket267// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0268// CHECK-NEXT:{{^}} ^269 270s_mov_b64 s[10:11], [s0,s1271// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket272// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s1273// CHECK-NEXT:{{^}} ^274 275image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D276// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket277// CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D278// CHECK-NEXT:{{^}} ^279 280image_load_mip v[253:255], [v255, v254281// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket282// CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254283// CHECK-NEXT:{{^}} ^284 285//==============================================================================286// expected a counter name287 288s_waitcnt vmcnt(0) & expcnt(0) & 1289// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name290// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & 1291// CHECK-NEXT:{{^}} ^292 293s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)&294// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name295// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)&296// CHECK-NEXT:{{^}} ^297 298s_waitcnt vmcnt(0) & expcnt(0) 1299// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name300// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) 1301// CHECK-NEXT:{{^}} ^302 303s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0),304// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name305// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0),306// CHECK-NEXT:{{^}} ^307 308//==============================================================================309// expected a format string310 311tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[]312// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a format string313// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[]314// CHECK-NEXT:{{^}} ^315 316//==============================================================================317// expected a left parenthesis318 319s_waitcnt vmcnt(0) & expcnt(0) & x320// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis321// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & x322// CHECK-NEXT:{{^}} ^323 324//==============================================================================325// expected a left square bracket326 327v_pk_add_u16 v1, v2, v3 op_sel:328// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left square bracket329// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:330// CHECK-NEXT:{{^}} ^331 332//==============================================================================333// expected a register334 335image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm336// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register337// CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm338// CHECK-NEXT:{{^}} ^339 340image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm341// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register342// CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm343// CHECK-NEXT:{{^}} ^344 345//==============================================================================346// expected a register or a list of registers347 348s_mov_b32 s1, [s0, 1349// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register or a list of registers350// CHECK-NEXT:{{^}}s_mov_b32 s1, [s0, 1351// CHECK-NEXT:{{^}} ^352 353//==============================================================================354// expected a single 32-bit register355 356s_mov_b64 s[10:11], [s0,s[2:3]]357// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a single 32-bit register358// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s[2:3]]359// CHECK-NEXT:{{^}} ^360 361//==============================================================================362// expected a string363 364ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)365// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a string366// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)367// CHECK-NEXT:{{^}} ^368 369//==============================================================================370// expected a swizzle mode371 372ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)373// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a swizzle mode374// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)375// CHECK-NEXT:{{^}} ^376 377//==============================================================================378// expected absolute expression379 380s_waitcnt vmcnt(x)381// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression382// CHECK-NEXT:{{^}}s_waitcnt vmcnt(x)383// CHECK-NEXT:{{^}} ^384 385tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]386// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression387// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]388// CHECK-NEXT:{{^}} ^389 390tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52391// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression392// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52393// CHECK-NEXT:{{^}} ^394 395tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]396// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression397// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]398// CHECK-NEXT:{{^}} ^399 400v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]401// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression402// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]403// CHECK-NEXT:{{^}} ^404 405v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0406// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression407// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0408// CHECK-NEXT:{{^}} ^409 410v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0411// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression412// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0413// CHECK-NEXT:{{^}} ^414 415//==============================================================================416// expected a message name or an absolute expression417 418s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)419// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a message name or an absolute expression420// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)421// CHECK-NEXT:{{^}} ^422 423//==============================================================================424// expected a register name or an absolute expression425 426s_setreg_b32 hwreg(HW_REG_WRONG), s2427// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register name or an absolute expression428// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(HW_REG_WRONG), s2429// CHECK-NEXT:{{^}} ^430 431//==============================================================================432// expected a sendmsg macro or an absolute expression433 434s_sendmsg undef435// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a sendmsg macro or an absolute expression436// CHECK-NEXT:{{^}}s_sendmsg undef437// CHECK-NEXT:{{^}} ^438 439//==============================================================================440// expected a swizzle macro or an absolute expression441 442ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)443// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a swizzle macro or an absolute expression444// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)445// CHECK-NEXT:{{^}} ^446 447//==============================================================================448// expected a hwreg macro or an absolute expression449 450s_setreg_b32 undef, s2451// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a hwreg macro, structured immediate or an absolute expression452// CHECK-NEXT:{{^}}s_setreg_b32 undef, s2453// CHECK-NEXT:{{^}} ^454 455//==============================================================================456// expected an 11-bit unsigned offset457 458flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc459// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 11-bit unsigned offset460// CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc461// CHECK-NEXT:{{^}} ^462 463//==============================================================================464// expected an absolute expression465 466v_ceil_f32 v1, abs(u)467// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression468// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(u)469// CHECK-NEXT:{{^}} ^470 471v_ceil_f32 v1, neg(u)472// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression473// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(u)474// CHECK-NEXT:{{^}} ^475 476v_ceil_f32 v1, |u|477// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression478// CHECK-NEXT:{{^}}v_ceil_f32 v1, |u|479// CHECK-NEXT:{{^}} ^480 481v_mov_b32_sdwa v1, sext(u)482// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression483// CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, sext(u)484// CHECK-NEXT:{{^}} ^485 486//==============================================================================487// expected a valid identifier or number in a valid range488 489v_mov_b32_sdwa v5, v1 dst_sel:490// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression491// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:492// CHECK-NEXT:{{^}} ^493 494v_mov_b32_sdwa v5, v1 dst_sel:0a495// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction496// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:0a497// CHECK-NEXT:{{^}} ^498 499v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1x500// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_sel value501// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1502// CHECK-NEXT:{{^}} ^503 504v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]505// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression506// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]507// CHECK-NEXT:{{^}} ^508 509v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:XXX510// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value511// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:XXX512// CHECK-NEXT:{{^}} ^513 514v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:3515// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value516// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:3517// CHECK-NEXT:{{^}} ^518 519v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:-1520// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value521// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:-1522// CHECK-NEXT:{{^}} ^523 524//==============================================================================525// expected an opening square bracket526 527v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)528// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an opening square bracket529// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)530// CHECK-NEXT:{{^}} ^531 532v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0533// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an opening square bracket534// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0535// CHECK-NEXT:{{^}} ^536 537//==============================================================================538// expected an operation name or an absolute expression539 540s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)541// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an operation name or an absolute expression542// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)543// CHECK-NEXT:{{^}} ^544 545//==============================================================================546// failed parsing operand.547 548v_ceil_f16 v0, abs(neg(1))549// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand.550// CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1))551// CHECK-NEXT:{{^}} ^552 553//==============================================================================554// first register index should not exceed second index555 556s_mov_b64 s[10:11], s[1:0]557// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: first register index should not exceed second index558// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], s[1:0]559// CHECK-NEXT:{{^}} ^560 561//==============================================================================562// group size must be a power of two563 564ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)565// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two566// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)567// CHECK-NEXT:{{^}} ^568 569ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)570// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two571// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)572// CHECK-NEXT:{{^}} ^573 574ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)575// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two576// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)577// CHECK-NEXT:{{^}} ^578 579//==============================================================================580// group size must be in the interval [1,16]581 582ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)583// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be in the interval [1,16]584// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)585// CHECK-NEXT:{{^}} ^586 587//==============================================================================588// group size must be in the interval [2,32]589 590ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)591// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be in the interval [2,32]592// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)593// CHECK-NEXT:{{^}} ^594 595//==============================================================================596// image address size does not match dim and a16597 598image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D599// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: image address size does not match dim and a16600// CHECK-NEXT:{{^}}image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D601// CHECK-NEXT:{{^}}^602 603//==============================================================================604// image data size does not match dmask, d16 and tfe605 606image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D607// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: image data size does not match dmask, d16 and tfe608// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D609// CHECK-NEXT:{{^}}^610 611//==============================================================================612// instruction must use glc613 614flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047615// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must use glc616// CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047617// CHECK-NEXT:{{^}}^618 619//==============================================================================620// instruction not supported on this GPU621 622s_cbranch_join 1623// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU624// CHECK-NEXT:{{^}}s_cbranch_join 1625// CHECK-NEXT:{{^}}^626 627//==============================================================================628// invalid bit offset: only 5-bit values are legal629 630s_getreg_b32 s2, hwreg(3,32,32)631// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid bit offset: only 5-bit values are legal632// CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(3,32,32)633// CHECK-NEXT:{{^}} ^634 635//==============================================================================636// invalid bitfield width: only values from 1 to 32 are legal637 638s_setreg_b32 hwreg(3,0,33), s2639// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid bitfield width: only values from 1 to 32 are legal640// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(3,0,33), s2641// CHECK-NEXT:{{^}} ^642 643//==============================================================================644// invalid hardware register: only 6-bit values are legal645 646s_setreg_b32 hwreg(0x40), s2647// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: only 6-bit values are legal648// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(0x40), s2649// CHECK-NEXT:{{^}} ^650 651//==============================================================================652// invalid counter name x653 654s_waitcnt vmcnt(0) & expcnt(0) x(0)655// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid counter name x656// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) x(0)657// CHECK-NEXT:{{^}} ^658 659//==============================================================================660// invalid dim value661 662image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D663// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value664// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D665// CHECK-NEXT:{{^}} ^666 667image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc668// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value669// CHECK-NEXT:{{^}}image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc670// CHECK-NEXT:{{^}} ^671 672image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D673// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value674// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D675// CHECK-NEXT:{{^}} ^676 677//==============================================================================678// invalid dst_sel value679 680v_mov_b32_sdwa v5, v1 dst_sel:WORD681// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_sel value682// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:WORD683// CHECK-NEXT:{{^}} ^684 685//==============================================================================686// invalid dst_unused value687 688v_mov_b32_sdwa v5, v1 dst_unused:UNUSED689// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value690// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_unused:UNUSED691// CHECK-NEXT:{{^}} ^692 693//==============================================================================694// invalid exp target695 696exp invalid_target_10 v3, v2, v1, v0697// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid exp target698// CHECK-NEXT:{{^}}exp invalid_target_10 v3, v2, v1, v0699// CHECK-NEXT:{{^}} ^700 701exp pos00 v3, v2, v1, v0702// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid exp target703// CHECK-NEXT:{{^}}exp pos00 v3, v2, v1, v0704// CHECK-NEXT:{{^}} ^705 706//==============================================================================707// invalid immediate: only 16-bit values are legal708 709s_setreg_b32 0x1f803, s2710// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid immediate: only 16-bit values are legal711// CHECK-NEXT:{{^}}s_setreg_b32 0x1f803, s2712// CHECK-NEXT:{{^}} ^713 714//==============================================================================715// invalid instruction716 717v_dot_f32_f16 v0, v1, v2718// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid instruction719// CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2720// CHECK-NEXT:{{^}}^721 722//==============================================================================723// invalid interpolation attribute724 725v_interp_p2_f32 v0, v1, att726// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid interpolation attribute727// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, att728// CHECK-NEXT:{{^}} ^729 730//==============================================================================731// invalid interpolation slot732 733v_interp_mov_f32 v8, p1, attr0.x734// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid interpolation slot735// CHECK-NEXT:{{^}}v_interp_mov_f32 v8, p1, attr0.x736// CHECK-NEXT:{{^}} ^737 738//==============================================================================739// invalid mask740 741ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")742// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid mask743// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")744// CHECK-NEXT:{{^}} ^745 746//==============================================================================747// invalid message id748 749s_sendmsg sendmsg(-1)750// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message id751// CHECK-NEXT:{{^}}s_sendmsg sendmsg(-1)752// CHECK-NEXT:{{^}} ^753 754//==============================================================================755// invalid message stream id756 757s_sendmsg sendmsg(2, 2, 4)758// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message stream id759// CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 4)760// CHECK-NEXT:{{^}} ^761 762s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)763// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message stream id764// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)765// CHECK-NEXT:{{^}} ^766 767//==============================================================================768// invalid mul value.769 770v_cvt_f64_i32 v[5:6], s1 mul:3771// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid mul value.772// CHECK-NEXT:{{^}}v_cvt_f64_i32 v[5:6], s1 mul:3773// CHECK-NEXT:{{^}} ^774 775//==============================================================================776// invalid or missing interpolation attribute channel777 778v_interp_p2_f32 v0, v1, attr0.q779// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or missing interpolation attribute channel780// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr0.q781// CHECK-NEXT:{{^}} ^782 783//==============================================================================784// invalid or missing interpolation attribute number785 786v_interp_p2_f32 v7, v1, attr.x787// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or missing interpolation attribute number788// CHECK-NEXT:{{^}}v_interp_p2_f32 v7, v1, attr.x789// CHECK-NEXT:{{^}} ^790 791//==============================================================================792// invalid op_sel operand793 794v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]795// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand796// CHECK-NEXT:{{^}}v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]797// CHECK-NEXT:{{^}} ^798 799//==============================================================================800// invalid op_sel value.801 802v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]803// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel value.804// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]805// CHECK-NEXT:{{^}} ^806 807//==============================================================================808// invalid operand (violates constant bus restrictions)809 810v_ashrrev_i64 v[0:1], 0x100, s[0:1]811// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)812// CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], 0x100, s[0:1]813// CHECK-NEXT:{{^}} ^814 815v_ashrrev_i64 v[0:1], s3, s[0:1]816// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)817// CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], s3, s[0:1]818// CHECK-NEXT:{{^}} ^819 820v_bfe_u32 v0, s1, 0x3039, s2821// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)822// CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, 0x3039, s2823// CHECK-NEXT:{{^}} ^824 825v_bfe_u32 v0, s1, s2, s3826// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)827// CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, s2, s3828// CHECK-NEXT:{{^}} ^829 830v_div_fmas_f32 v5, s3, 0x123, v3831// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)832// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, 0x123, v3833// CHECK-NEXT:{{^}} ^834 835v_div_fmas_f32 v5, s3, v3, 0x123836// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)837// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, v3, 0x123838// CHECK-NEXT:{{^}} ^839 840v_div_fmas_f32 v5, 0x123, v3, s3841// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)842// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, 0x123, v3, s3843// CHECK-NEXT:{{^}} ^844 845v_div_fmas_f32 v5, s3, s4, v3846// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)847// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, s4, v3848// CHECK-NEXT:{{^}} ^849 850//==============================================================================851// invalid operand for instruction852 853buffer_load_dword v[5:6], off, s[8:11], s3 tfe lds854// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction855// CHECK-NEXT:{{^}}buffer_load_dword v[5:6], off, s[8:11], s3 tfe lds856// CHECK-NEXT:{{^}} ^857 858exp mrt0 0x12345678, v0, v0, v0859// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction860// CHECK-NEXT:{{^}}exp mrt0 0x12345678, v0, v0, v0861// CHECK-NEXT:{{^}} ^862 863v_cmp_eq_f32 s[0:1], private_base, s0864// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction865// CHECK-NEXT:{{^}}v_cmp_eq_f32 s[0:1], private_base, s0866// CHECK-NEXT:{{^}} ^867 868//==============================================================================869// invalid operation id870 871s_sendmsg sendmsg(15, -1)872// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id873// CHECK-NEXT:{{^}}s_sendmsg sendmsg(15, -1)874// CHECK-NEXT:{{^}} ^875 876//==============================================================================877// invalid or unsupported register size878 879s_mov_b64 s[0:17], -1880// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or unsupported register size881// CHECK-NEXT:{{^}}s_mov_b64 s[0:17], -1882// CHECK-NEXT:{{^}} ^883 884//==============================================================================885// invalid register alignment886 887s_load_dwordx4 s[1:4], s[2:3], s4888// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register alignment889// CHECK-NEXT:{{^}}s_load_dwordx4 s[1:4], s[2:3], s4890// CHECK-NEXT:{{^}} ^891 892//==============================================================================893// invalid register index894 895s_mov_b32 s1, s[0:-1]896// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register index897// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0:-1]898// CHECK-NEXT:{{^}} ^899 900v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]901// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register index902// CHECK-NEXT:{{^}}v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]903// CHECK-NEXT:{{^}} ^904 905//==============================================================================906// invalid register name907 908s_mov_b64 s[10:11], [x0,s1]909// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register name910// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [x0,s1]911// CHECK-NEXT:{{^}} ^912 913//==============================================================================914// invalid row_share value915 916v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0917// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid row_share value918// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0919// CHECK-NEXT:{{^}} ^920 921v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0922// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid row_share value923// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0924// CHECK-NEXT:{{^}} ^925 926//==============================================================================927// invalid syntax, expected 'neg' modifier928 929v_ceil_f32 v0, --1930// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid syntax, expected 'neg' modifier931// CHECK-NEXT:{{^}}v_ceil_f32 v0, --1932// CHECK-NEXT:{{^}} ^933 934//==============================================================================935// lane id must be in the interval [0,group size - 1]936 937ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)938// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lane id must be in the interval [0,group size - 1]939// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)940// CHECK-NEXT:{{^}} ^941 942//==============================================================================943// lds_direct cannot be used with this instruction944 945v_ashrrev_i16 v0, lds_direct, v0946// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction947// CHECK-NEXT:{{^}}v_ashrrev_i16 v0, lds_direct, v0948// CHECK-NEXT:{{^}} ^949 950v_ashrrev_i16 v0, v1, lds_direct951// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction952// CHECK-NEXT:{{^}}v_ashrrev_i16 v0, v1, lds_direct953// CHECK-NEXT:{{^}} ^954 955v_mov_b32_sdwa v1, src_lds_direct dst_sel:DWORD956// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction957// CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, src_lds_direct dst_sel:DWORD958// CHECK-NEXT:{{^}} ^959 960v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD961// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction962// CHECK-NEXT:{{^}}v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD963// CHECK-NEXT:{{^}} ^964 965//==============================================================================966// lds_direct may be used as src0 only967 968v_add_f32 v5, v1, lds_direct969// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct may be used as src0 only970// CHECK-NEXT:{{^}}v_add_f32 v5, v1, lds_direct971// CHECK-NEXT:{{^}} ^972 973//==============================================================================974// message does not support operations975 976s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)977// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: message does not support operations978// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)979// CHECK-NEXT:{{^}} ^980 981//==============================================================================982// message operation does not support streams983 984s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)985// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: message operation does not support streams986// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)987// CHECK-NEXT:{{^}} ^988 989//==============================================================================990// missing message operation991 992s_sendmsg sendmsg(MSG_SYSMSG)993// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing message operation994// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_SYSMSG)995// CHECK-NEXT:{{^}} ^996 997//==============================================================================998// missing register index999 1000s_mov_b64 s[10:11], [s1001// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing register index1002// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s1003// CHECK-NEXT:{{^}} ^1004 1005s_mov_b64 s[10:11], [s,s1]1006// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing register index1007// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s,s1]1008// CHECK-NEXT:{{^}} ^1009 1010//==============================================================================1011// not a valid operand.1012 1013s_branch offset:11014// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.1015// CHECK-NEXT:{{^}}s_branch offset:11016// CHECK-NEXT:{{^}} ^1017 1018v_mov_b32 v0, v0 row_bcast:01019// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.1020// CHECK-NEXT:{{^}}v_mov_b32 v0, v0 row_bcast:01021// CHECK-NEXT:{{^}} ^1022 1023//==============================================================================1024// only one unique literal operand is allowed1025 1026s_and_b32 s2, 0x12345678, 0x123456791027// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1028// CHECK-NEXT:{{^}}s_and_b32 s2, 0x12345678, 0x123456791029// CHECK-NEXT:{{^}} ^1030 1031v_add_f64 v[0:1], 1.23456, -abs(1.2345)1032// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1033// CHECK-NEXT:{{^}}v_add_f64 v[0:1], 1.23456, -abs(1.2345)1034// CHECK-NEXT:{{^}} ^1035 1036v_min3_i16 v5, 0x5678, 0x5678, 0x56791037// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1038// CHECK-NEXT:{{^}}v_min3_i16 v5, 0x5678, 0x5678, 0x56791039// CHECK-NEXT:{{^}} ^1040 1041v_pk_add_f16 v1, 25.0, 25.11042// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1043// CHECK-NEXT:{{^}}v_pk_add_f16 v1, 25.0, 25.11044// CHECK-NEXT:{{^}} ^1045 1046v_fma_mix_f32 v5, 0x7c, 0x7b, 11047// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1048// CHECK-NEXT:{{^}}v_fma_mix_f32 v5, 0x7c, 0x7b, 11049// CHECK-NEXT:{{^}} ^1050 1051v_pk_add_i16 v5, 0x7c, 0x40001052// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1053// CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x7c, 0x40001054// CHECK-NEXT:{{^}} ^1055 1056v_pk_add_i16 v5, 0x4400, 0x40001057// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1058// CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x4400, 0x40001059// CHECK-NEXT:{{^}} ^1060 1061v_bfe_u32 v0, v2, 123, undef1062// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1063// CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, 123, undef1064// CHECK-NEXT:{{^}} ^1065 1066v_bfe_u32 v0, v2, undef, 1231067// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed1068// CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, undef, 1231069// CHECK-NEXT:{{^}} ^1070 1071//==============================================================================1072// out of bounds interpolation attribute number1073 1074v_interp_p1_f32 v0, v1, attr64.w1075// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: out of bounds interpolation attribute number1076// CHECK-NEXT:{{^}}v_interp_p1_f32 v0, v1, attr64.w1077// CHECK-NEXT:{{^}} ^1078 1079//==============================================================================1080// out of range format1081 1082tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 01083// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: out of range format1084// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 01085// CHECK-NEXT:{{^}} ^1086 1087//==============================================================================1088// register does not fit in the list1089 1090s_mov_b64 s[10:11], [exec,exec_lo]1091// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register does not fit in the list1092// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec,exec_lo]1093// CHECK-NEXT:{{^}} ^1094 1095s_mov_b64 s[10:11], [exec_lo,exec]1096// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register does not fit in the list1097// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec_lo,exec]1098// CHECK-NEXT:{{^}} ^1099 1100//==============================================================================1101// register index is out of range1102 1103s_add_i32 s106, s0, s11104// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range1105// CHECK-NEXT:{{^}}s_add_i32 s106, s0, s11106// CHECK-NEXT:{{^}} ^1107 1108s_load_dwordx16 s[100:115], s[2:3], s41109// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range1110// CHECK-NEXT:{{^}}s_load_dwordx16 s[100:115], s[2:3], s41111// CHECK-NEXT:{{^}} ^1112 1113s_mov_b32 ttmp16, 01114// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range1115// CHECK-NEXT:{{^}}s_mov_b32 ttmp16, 01116// CHECK-NEXT:{{^}} ^1117 1118v_add_nc_i32 v256, v0, v11119// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range1120// CHECK-NEXT:{{^}}v_add_nc_i32 v256, v0, v11121// CHECK-NEXT:{{^}} ^1122 1123//==============================================================================1124// register not available on this GPU1125 1126s_and_b32 ttmp9, tma_hi, 0x0000ffff1127// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: tma_hi register not available on this GPU1128// CHECK-NEXT:{{^}}s_and_b32 ttmp9, tma_hi, 0x0000ffff1129// CHECK-NEXT:{{^}} ^1130 1131s_mov_b32 flat_scratch, -11132// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch register not available on this GPU1133// CHECK-NEXT:{{^}}s_mov_b32 flat_scratch, -11134// CHECK-NEXT:{{^}} ^1135 1136//==============================================================================1137// registers in a list must be of the same kind1138 1139s_mov_b64 s[10:11], [a0,v1]1140// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must be of the same kind1141// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,v1]1142// CHECK-NEXT:{{^}} ^1143 1144//==============================================================================1145// registers in a list must have consecutive indices1146 1147s_mov_b64 s[10:11], [a0,a2]1148// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices1149// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,a2]1150// CHECK-NEXT:{{^}} ^1151 1152s_mov_b64 s[10:11], [s0,s0]1153// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices1154// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s0]1155// CHECK-NEXT:{{^}} ^1156 1157s_mov_b64 s[10:11], [s2,s1]1158// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices1159// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s2,s1]1160// CHECK-NEXT:{{^}} ^1161 1162//==============================================================================1163// source operand must be a VGPR1164 1165v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD1166// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR1167// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD1168// CHECK-NEXT:{{^}} ^1169 1170v_movrels_b32_sdwa v0, s01171// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR1172// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, s01173// CHECK-NEXT:{{^}} ^1174 1175v_movrels_b32_sdwa v0, shared_base1176// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR1177// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, shared_base1178// CHECK-NEXT:{{^}} ^1179 1180//==============================================================================1181// invalid hardware register: not supported on this GPU1182 1183s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)1184// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU1185// CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)1186// CHECK-NEXT:{{^}} ^1187 1188//==============================================================================1189// too few operands for instruction1190 1191tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]1192// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction1193// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]1194// CHECK-NEXT:{{^}}^1195 1196v_add_f32_e64 v0, v11197// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction1198// CHECK-NEXT:{{^}}v_add_f32_e64 v0, v11199// CHECK-NEXT:{{^}}^1200 1201buffer_load_dword off, s[8:11], s31202// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction1203// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s31204// CHECK-NEXT:{{^}}^1205 1206buffer_load_dword off, s[8:11], s3 offset:11207// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction1208// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3 offset:11209// CHECK-NEXT:{{^}}^1210 1211//==============================================================================1212// too large value for expcnt1213 1214s_waitcnt expcnt(8)1215// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for expcnt1216// CHECK-NEXT:{{^}}s_waitcnt expcnt(8)1217// CHECK-NEXT:{{^}} ^1218 1219//==============================================================================1220// too large value for lgkmcnt1221 1222s_waitcnt lgkmcnt(64)1223// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for lgkmcnt1224// CHECK-NEXT:{{^}}s_waitcnt lgkmcnt(64)1225// CHECK-NEXT:{{^}} ^1226 1227//==============================================================================1228// too large value for vmcnt1229 1230s_waitcnt vmcnt(64)1231// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for vmcnt1232// CHECK-NEXT:{{^}}s_waitcnt vmcnt(64)1233// CHECK-NEXT:{{^}} ^1234 1235//==============================================================================1236// unknown token in expression1237 1238ds_swizzle_b32 v8, v2 offset:1239// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1240// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:1241// CHECK-NEXT:{{^}} ^1242 1243s_sendmsg sendmsg(1 -)1244// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1245// CHECK-NEXT:{{^}}s_sendmsg sendmsg(1 -)1246// CHECK-NEXT:{{^}} ^1247 1248tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s01249// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1250// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s01251// CHECK-NEXT:{{^}} ^1252 1253tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s01254// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1255// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s01256// CHECK-NEXT:{{^}} ^1257 1258v_pk_add_u16 v1, v2, v3 op_sel:[1259// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1260// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[1261// CHECK-NEXT:{{^}} ^1262 1263v_pk_add_u16 v1, v2, v3 op_sel:[,0]1264// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1265// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,0]1266// CHECK-NEXT:{{^}} ^1267 1268v_pk_add_u16 v1, v2, v3 op_sel:[,]1269// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1270// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,]1271// CHECK-NEXT:{{^}} ^1272 1273v_pk_add_u16 v1, v2, v3 op_sel:[0,]1274// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1275// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,]1276// CHECK-NEXT:{{^}} ^1277 1278v_pk_add_u16 v1, v2, v3 op_sel:[]1279// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression1280// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[]1281// CHECK-NEXT:{{^}} ^1282 1283//==============================================================================1284// unsupported format1285 1286tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT]1287// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unsupported format1288// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT]1289// CHECK-NEXT:{{^}} ^1290 1291//==============================================================================1292// expected vertical bar1293 1294v_ceil_f32 v1, |1+1|1295// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected vertical bar1296// CHECK-NEXT:{{^}}v_ceil_f32 v1, |1+1|1297// CHECK-NEXT:{{^}} ^1298 1299//==============================================================================1300// expected left paren after neg1301 1302v_ceil_f32 v1, neg-(v2)1303// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after neg1304// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg-(v2)1305// CHECK-NEXT:{{^}} ^1306 1307//==============================================================================1308// expected left paren after abs1309 1310v_ceil_f32 v1, abs-(v2)1311// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after abs1312// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs-(v2)1313// CHECK-NEXT:{{^}} ^1314 1315//==============================================================================1316// expected left paren after sext1317 1318v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD1319// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after sext1320// CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD1321// CHECK-NEXT:{{^}} ^1322 1323//==============================================================================1324// expected closing parentheses1325 1326v_ceil_f32 v1, abs(v2]1327// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses1328// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(v2]1329// CHECK-NEXT:{{^}} ^1330 1331v_ceil_f32 v1, neg(v2]1332// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses1333// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(v2]1334// CHECK-NEXT:{{^}} ^1335 1336v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD1337// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses1338// CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD1339// CHECK-NEXT:{{^}} ^1340 1341//==============================================================================1342// expected a left parentheses1343 1344ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3]1345// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parentheses1346// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3]1347// CHECK-NEXT:{{^}} ^1348 1349//==============================================================================1350// expected an absolute expression or a label1351 1352s_branch 1+x1353// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression or a label1354// CHECK-NEXT:{{^}}s_branch 1+x1355// CHECK-NEXT:{{^}} ^1356 1357//==============================================================================1358// expected a 16-bit offset1359 1360ds_swizzle_b32 v8, v2 offset:0x100001361// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 16-bit offset1362// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:0x100001363// CHECK-NEXT:{{^}} ^1364 1365//==============================================================================1366// not a valid operand1367 1368v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_01369// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.1370// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_01371// CHECK-NEXT:{{^}} ^1372 1373//==============================================================================1374// TFE modifier has no meaning for store instructions1375 1376buffer_store_dword v[1:2], off, s[12:15], s4 tfe1377// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: TFE modifier has no meaning for store instructions1378// CHECK-NEXT:{{^}}buffer_store_dword v[1:2], off, s[12:15], s4 tfe1379// CHECK-NEXT:{{^}} ^1380