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1// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 52// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s3// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s4// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefixes=W32-ERR,GFX11-ERR --implicit-check-not=error: %s5// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefixes=W64-ERR,GFX11-ERR --implicit-check-not=error: %s6 7//===----------------------------------------------------------------------===//8// HW correctly handles fp inline constants for src2 (they have f16 type).9// Check that inline constants are not converted to literals.10//===----------------------------------------------------------------------===//11 12v_cmp_class_f16_e64 s[10:11], v1.l, 0.513// W64: v_cmp_class_f16_e64 s[10:11], v1.l, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]14// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction15 16v_cmp_class_f16_e64 s10, v1.l, 0.517// W32: v_cmp_class_f16_e64 s10, v1.l, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]18// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction19 20v_cmpx_class_f16_e64 v1.l, 0.521// GFX11: v_cmpx_class_f16_e64 v1.l, 0.5 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]22 23//===----------------------------------------------------------------------===//24// src0 and src2 are packed operands.25// Check that op_sel is not allowed with these operands.26//===----------------------------------------------------------------------===//27 28v_dot2_f16_f16_e64 v0.l, v1.h, v2, v3.l29// GFX11-ERR: :[[@LINE-1]]:26: error: invalid operand for instruction30 31v_dot2_f16_f16_e64_dpp v0.l, v1, v2.h, v3.l dpp8:[0,1,2,3,4,4,4,4]32// GFX11-ERR: :[[@LINE-1]]:34: error: invalid operand for instruction33 34v_dot2_f16_f16_e64_dpp v0.l, v1.h, v2, v3.l quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:135// GFX11-ERR: :[[@LINE-1]]:30: error: invalid operand for instruction36 37v_dot2_bf16_bf16_e64 v0.l, v1, v2.h, v3.l38// GFX11-ERR: :[[@LINE-1]]:32: error: invalid operand for instruction39 40v_dot2_bf16_bf16_e64_dpp v0.l, v1.h, v2, v3.l dpp8:[0,1,2,3,4,4,4,4]41// GFX11-ERR: :[[@LINE-1]]:32: error: invalid operand for instruction42 43v_dot2_bf16_bf16_e64_dpp v0.l, v1, v2.h, v3.l quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:144// GFX11-ERR: :[[@LINE-1]]:36: error: invalid operand for instruction45 46//===----------------------------------------------------------------------===//47// src0 and src1 are vector operands.48// Check that SGPRs are not allowed for these operands.49//===----------------------------------------------------------------------===//50 51v_dot2_f16_f16_e64_dpp v0.l, s1, v2, v3.l dpp8:[0,1,2,3,4,4,4,4]52// GFX11-ERR: :[[@LINE-1]]:30: error: invalid operand for instruction53 54v_dot2_f16_f16_e64_dpp v0.l, v1, s2, v3.l dpp8:[0,1,2,3,4,4,4,4]55// GFX11-ERR: :[[@LINE-1]]:34: error: invalid operand for instruction56 57v_dot2_f16_f16_e64_dpp v0.l, s1, v2, v3.l quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:158// GFX11-ERR: :[[@LINE-1]]:30: error: invalid operand for instruction59 60v_dot2_f16_f16_e64_dpp v0.l, v1, s2, v3.l quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:161// GFX11-ERR: :[[@LINE-1]]:34: error: invalid operand for instruction62 63v_dot2_bf16_bf16_e64_dpp v0.l, s1, v2, v3.l dpp8:[0,1,2,3,4,4,4,4]64// GFX11-ERR: :[[@LINE-1]]:32: error: invalid operand for instruction65 66v_dot2_bf16_bf16_e64_dpp v0.l, v1, s2, v3.l dpp8:[0,1,2,3,4,4,4,4]67// GFX11-ERR: :[[@LINE-1]]:36: error: invalid operand for instruction68 69v_dot2_bf16_bf16_e64_dpp v0.l, s1, v2, v3.l quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x070// GFX11-ERR: :[[@LINE-1]]:32: error: invalid operand for instruction71 72v_dot2_bf16_bf16_e64_dpp v0.l, v1, s2, v3.l quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x073// GFX11-ERR: :[[@LINE-1]]:36: error: invalid operand for instruction74 75// Ensure bits 8-15 are not zeroed out and .h which should be present on src0 and dst are present.76v_mul_f16_e64 v5.h, v1.h, v2.l77// GFX11: v_mul_f16_e64 v5.h, v1.h, v2.l op_sel:[1,0,1] ; encoding: [0x05,0x48,0x35,0xd5,0x01,0x05,0x02,0x00]78