36 lines · plain
1// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --implicit-check-not=error: %s2// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s3 4v_add_co_u32_e32 v2, vcc, s0, v25// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported6 7v_ashrrev_i16_e32 v1, v2, v38// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported9 10v_lshlrev_b16_e32 v1, v2, v311// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported12 13v_lshrrev_b16_e32 v1, v2, v314// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported15 16v_max_i16_e32 v1, v2, v317// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported18 19v_max_u16_e32 v1, v2, v320// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported21 22v_min_i16_e32 v1, v2, v323// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported24 25v_min_u16_e32 v1, v2, v326// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported27 28v_mul_lo_u16_e32 v1, v2, v329// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported30 31v_sub_co_u32_e32 v2, vcc, s0, v232// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported33 34v_subrev_co_u32_e32 v2, vcc, s0, v235// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported36