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1// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 %s 2>&1 | FileCheck %s -check-prefix=GFX12 --implicit-check-not=error: --strict-whitespace2 3//===----------------------------------------------------------------------===//4// A VOPD instruction can use only one literal.5//===----------------------------------------------------------------------===//6 7v_dual_mul_f32 v11, 0x24681357, v2 :: v_dual_mul_f32 v10, 0xbabe, v58// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed9// GFX12-NEXT:{{^}}v_dual_mul_f32 v11, 0x24681357, v2 :: v_dual_mul_f32 v10, 0xbabe, v510// GFX12-NEXT:{{^}} ^11 12//===----------------------------------------------------------------------===//13// When 2 different literals are specified, show the location14// of the last literal which is not a KImm, if any.15//===----------------------------------------------------------------------===//16 17v_dual_fmamk_f32 v122, v74, 0xa0172923, v161 :: v_dual_lshlrev_b32 v247, 0xbabe, v9918// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed19// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, v74, 0xa0172923, v161 :: v_dual_lshlrev_b32 v247, 0xbabe, v9920// GFX12-NEXT:{{^}} ^21 22v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xbabe23// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed24// GFX12-NEXT:{{^}}v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xbabe25// GFX12-NEXT:{{^}} ^26 27v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, 0xbabe, v1, 0xbabe28// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed29// GFX12-NEXT:{{^}}v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, 0xbabe, v1, 0xbabe30// GFX12-NEXT:{{^}} ^31 32v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0x1234, v16233// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed34// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0x1234, v16235// GFX12-NEXT:{{^}} ^36 37v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, s0, 0x1234, v16238// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed39// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, s0, 0x1234, v16240// GFX12-NEXT:{{^}} ^41 42//===----------------------------------------------------------------------===//43// Check that assembler detects a different literal regardless of its location.44//===----------------------------------------------------------------------===//45 46v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0x1234, v16247// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed48// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0x1234, v16249// GFX12-NEXT:{{^}} ^50 51v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0x1234, 0xdeadbeef, v16252// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed53// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0x1234, 0xdeadbeef, v16254// GFX12-NEXT:{{^}} ^55 56v_dual_fmamk_f32 v122, 0xdeadbeef, 0x1234, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0xdeadbeef, v16257// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed58// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, 0xdeadbeef, 0x1234, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0xdeadbeef, v16259// GFX12-NEXT:{{^}} ^60 61v_dual_fmamk_f32 v122, 0x1234, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0xdeadbeef, v16262// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed63// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, 0x1234, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0xdeadbeef, v16264// GFX12-NEXT:{{^}} ^65 66//===----------------------------------------------------------------------===//67// When 2 different literals are specified and all literals are KImm,68// show the location of the last KImm literal.69//===----------------------------------------------------------------------===//70 71v_dual_fmamk_f32 v122, s0, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, s0, 0x1234, v16272// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed73// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, s0, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, s0, 0x1234, v16274// GFX12-NEXT:{{^}} ^75 76//===----------------------------------------------------------------------===//77// A VOPD instruction cannot use more than 2 scalar operands78//===----------------------------------------------------------------------===//79 80// 2 different SGPRs + LITERAL81 82v_dual_fmaak_f32 v122, s74, v161, 2.741 :: v_dual_max_i32 v247, s75, v9883// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)84// GFX12-NEXT:{{^}}v_dual_fmaak_f32 v122, s74, v161, 2.741 :: v_dual_max_i32 v247, s75, v9885// GFX12-NEXT:{{^}} ^86 87v_dual_mov_b32 v247, s73 :: v_dual_fmaak_f32 v122, s74, v161, 2.74188// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)89// GFX12-NEXT:{{^}}v_dual_mov_b32 v247, s73 :: v_dual_fmaak_f32 v122, s74, v161, 2.74190// GFX12-NEXT:{{^}} ^91 92v_dual_fmamk_f32 v122, s0, 0xbabe, v161 :: v_dual_fmamk_f32 v123, s1, 0xbabe, v16293// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)94// GFX12-NEXT:{{^}}v_dual_fmamk_f32 v122, s0, 0xbabe, v161 :: v_dual_fmamk_f32 v123, s1, 0xbabe, v16295// GFX12-NEXT:{{^}} ^96 97// 2 different SGPRs + VCC98 99v_dual_add_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s2, v3100// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)101// GFX12-NEXT:{{^}}v_dual_add_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s2, v3102// GFX12-NEXT:{{^}} ^103 104v_dual_cndmask_b32 v6, s1, v3 :: v_dual_add_f32 v255, s2, v2105// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)106// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v6, s1, v3 :: v_dual_add_f32 v255, s2, v2107// GFX12-NEXT:{{^}} ^108 109v_dual_cndmask_b32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s2, v3110// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)111// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s2, v3112// GFX12-NEXT:{{^}} ^113 114v_dual_cndmask_b32 v1, s2, v3, vcc_lo :: v_dual_cndmask_b32 v2, s3, v4, vcc_lo115// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)116// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v1, s2, v3, vcc_lo :: v_dual_cndmask_b32 v2, s3, v4, vcc_lo117// GFX12-NEXT:{{^}} ^118 119// SGPR + LITERAL + VCC120 121v_dual_cndmask_b32 v255, s1, v2 :: v_dual_mov_b32 v254, 0xbabe122// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)123// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v255, s1, v2 :: v_dual_mov_b32 v254, 0xbabe124// GFX12-NEXT:{{^}} ^125 126v_dual_cndmask_b32 v255, 0xbabe, v2 :: v_dual_mov_b32 v254, s1127// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)128// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v255, 0xbabe, v2 :: v_dual_mov_b32 v254, s1129// GFX12-NEXT:{{^}} ^130 131v_dual_cndmask_b32 v255, s3, v2 :: v_dual_fmamk_f32 v254, v1, 0xbabe, v162132// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)133// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v255, s3, v2 :: v_dual_fmamk_f32 v254, v1, 0xbabe, v162134// GFX12-NEXT:{{^}} ^135 136v_dual_cndmask_b32 v255, v1, v2 :: v_dual_fmamk_f32 v254, s3, 0xbabe, v162137// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)138// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v255, v1, v2 :: v_dual_fmamk_f32 v254, s3, 0xbabe, v162139// GFX12-NEXT:{{^}} ^140 141// SGPR + VCC + VCC_LO142// This is a special case because implicit VCC operand has 64 bit size.143// SP3 does not accept this instruction as well.144 145v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, s1, v3146// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)147// GFX12-NEXT:{{^}}v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, s1, v3148// GFX12-NEXT:{{^}} ^149 150// FIXME: Error should be 'unsupported instruction'151v_dual_add_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3152// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode153// GFX12-NEXT:{{^}}v_dual_add_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3154// GFX12-NEXT:{{^}}^155 156v_dual_cndmask_b32 v255, v4, v2 :: v_dual_fmaak_f32 v7, v101, v3, 0xaf123456157// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: one dst register must be even and the other odd158// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v255, v4, v2 :: v_dual_fmaak_f32 v7, v101, v3, 0xaf123456159// GFX12-NEXT:{{^}} ^160 161v_dual_add_f32 v2, v2, v5 :: v_dual_mul_f32 v4, 130, v6162// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: one dst register must be even and the other odd163// GFX12-NEXT:{{^}}v_dual_add_f32 v2, v2, v5 :: v_dual_mul_f32 v4, 130, v6164// GFX12-NEXT:{{^}} ^165 166// Even though it could be represented as VOPD3, fmac reads its dst and bank constraints still apply to src2.167v_dual_fmac_f32 v255, s105, v2 :: v_dual_fmac_f32 v7, s1, v3168// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: one dst register must be even and the other odd169// GFX12-NEXT:{{^}}v_dual_fmac_f32 v255, s105, v2 :: v_dual_fmac_f32 v7, s1, v3170// GFX12-NEXT:{{^}} ^171 172// Destination should be distinct even if not checked for parity in VOPD3173v_dual_fmac_f32 v7, v4, v2 :: v_dual_fmac_f32 v7, v1, v3174// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: dst registers must be distinct175// GFX12-NEXT:{{^}}v_dual_fmac_f32 v7, v4, v2 :: v_dual_fmac_f32 v7, v1, v3176// GFX12-NEXT:{{^}} ^177 178v_dual_add_f32 v7, v4, v2 :: v_dual_add_f32 v7, v5, v3179// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: dst registers must be distinct180// GFX12-NEXT:{{^}}v_dual_add_f32 v7, v4, v2 :: v_dual_add_f32 v7, v5, v3181// GFX12-NEXT:{{^}} ^182 183//===----------------------------------------------------------------------===//184// A 64-bit operand shall not have bank conflicts with both subregs.185// There is also NO exception that a 64 bit operand can start whith the same186// register as 32 bit.187//===----------------------------------------------------------------------===//188v_dual_add_f64 v[2:3], v[4:5], v[8:9] :: v_dual_ashrrev_i32 v5, v8, v6189// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: src0 operands must use different VGPR banks190// GFX12-NEXT:{{^}}v_dual_add_f64 v[2:3], v[4:5], v[8:9] :: v_dual_ashrrev_i32 v5, v8, v6191// GFX12-NEXT:{{^}} ^192 193v_dual_add_f64 v[2:3], v[4:5], v[8:9] :: v_dual_ashrrev_i32 v5, v9, v6194// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: src0 operands must use different VGPR banks195// GFX12-NEXT:{{^}}v_dual_add_f64 v[2:3], v[4:5], v[8:9] :: v_dual_ashrrev_i32 v5, v9, v6196// GFX12-NEXT:{{^}} ^197 198v_dual_add_f64 v[2:3], v[4:5], v[8:9] :: v_dual_ashrrev_i32 v5, v4, v6199// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: src0 operands must use different VGPR banks200// GFX12-NEXT:{{^}}v_dual_add_f64 v[2:3], v[4:5], v[8:9] :: v_dual_ashrrev_i32 v5, v4, v6201// GFX12-NEXT:{{^}} ^202 203v_dual_add_f64 v[2:3], 1, v[8:9] :: v_dual_ashrrev_i32 v3, v7, v6204// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: dst registers must be distinct205// GFX12-NEXT:{{^}}v_dual_add_f64 v[2:3], 1, v[8:9] :: v_dual_ashrrev_i32 v3, v7, v6206// GFX12-NEXT:{{^}} ^207 208//===----------------------------------------------------------------------===//209// Literals not supported by VOPD3. Inline literals can only be encoded for210// src0, but not for vsrc1 or vsrc2.211//===----------------------------------------------------------------------===//212v_dual_add_f64 v[2:3], 100.0, v[8:9] :: v_dual_ashrrev_i32 v4, v7, v6213// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction214// GFX12-NEXT:{{^}}v_dual_add_f64 v[2:3], 100.0, v[8:9] :: v_dual_ashrrev_i32 v4, v7, v6215// GFX12-NEXT:{{^}} ^216 217v_dual_fma_f32 v255, s105, v2, v255 :: v_dual_fma_f32 v7, 1, 0, v8218// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction219// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, s105, v2, v255 :: v_dual_fma_f32 v7, 1, 0, v8220// GFX12-NEXT:{{^}} ^221 222v_dual_fma_f32 v255, s105, v2, v255 :: v_dual_fma_f32 v7, 1, v0, 0223// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction224// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, s105, v2, v255 :: v_dual_fma_f32 v7, 1, v0, 0225// GFX12-NEXT:{{^}} ^226 227//===----------------------------------------------------------------------===//228// Check that we properly detect bank conflicts if instruction is derived from229// VOP3.230//===----------------------------------------------------------------------===//231v_dual_fma_f32 v1, v4, v2, v3 :: v_dual_fma_f32 v3, v8, v7, v6232// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: src0 operands must use different VGPR banks233// GFX12-NEXT:{{^}}v_dual_fma_f32 v1, v4, v2, v3 :: v_dual_fma_f32 v3, v8, v7, v6234// GFX12-NEXT:{{^}} ^235 236v_dual_fma_f32 v1, v4, v2, v3 :: v_dual_fma_f32 v3, v5, v6, v8237// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: src1 operands must use different VGPR banks238// GFX12-NEXT:{{^}}v_dual_fma_f32 v1, v4, v2, v3 :: v_dual_fma_f32 v3, v5, v6, v8239// GFX12-NEXT:{{^}} ^240 241v_dual_fma_f32 v1, v4, v2, v3 :: v_dual_fma_f32 v3, v5, v8, v7242// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: src2 operands must use different VGPR banks243// GFX12-NEXT:{{^}}v_dual_fma_f32 v1, v4, v2, v3 :: v_dual_fma_f32 v3, v5, v8, v7244// GFX12-NEXT:{{^}} ^245 246v_dual_fma_f32 v1, v4, v2, v3 :: v_dual_fmac_f32 v7, v5, v8247// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: src2 operands must use different VGPR banks248// GFX12-NEXT:{{^}}v_dual_fma_f32 v1, v4, v2, v3 :: v_dual_fmac_f32 v7, v5, v8249// GFX12-NEXT:{{^}} ^250 251v_dual_fmac_f32 v7, v5, v8 :: v_dual_fma_f32 v1, v4, v2, v3252// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: src2 operands must use different VGPR banks253// GFX12-NEXT:{{^}}v_dual_fmac_f32 v7, v5, v8 :: v_dual_fma_f32 v1, v4, v2, v3254// GFX12-NEXT:{{^}} ^255 256//===----------------------------------------------------------------------===//257// ABS modifiers are not supported258//===----------------------------------------------------------------------===//259v_dual_fma_f32 v255, |s105|, v0, v1 :: v_dual_add_nc_u32 v7, s1, v0260// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: ABS not allowed in VOPD3 instructions261// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, |s105|, v0, v1 :: v_dual_add_nc_u32 v7, s1, v0262// GFX12-NEXT:{{^}} ^263 264v_dual_fma_f32 v255, s105, abs(v0), v1 :: v_dual_fma_f32 v7, s1, v0, v8265// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: ABS not allowed in VOPD3 instructions266// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, s105, abs(v0), v1 :: v_dual_fma_f32 v7, s1, v0, v8267// GFX12-NEXT:{{^}} ^268 269v_dual_fma_f32 v255, s105, v0, |v1| :: v_dual_fma_f32 v7, s1, v0, v8270// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: ABS not allowed in VOPD3 instructions271// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, s105, v0, |v1| :: v_dual_fma_f32 v7, s1, v0, v8272// GFX12-NEXT:{{^}} ^273 274v_dual_add_nc_u32 v255, s105, v0 :: v_dual_fma_f32 v7, |1|, v0, v8275// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: ABS not allowed in VOPD3 instructions276// GFX12-NEXT:{{^}}v_dual_add_nc_u32 v255, s105, v0 :: v_dual_fma_f32 v7, |1|, v0, v8277// GFX12-NEXT:{{^}} ^278 279v_dual_fma_f32 v255, s105, v0, v1 :: v_dual_fma_f32 v7, s1, -|v0|, v8280// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: ABS not allowed in VOPD3 instructions281// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, s105, v0, v1 :: v_dual_fma_f32 v7, s1, -|v0|, v8282// GFX12-NEXT:{{^}} ^283 284v_dual_fma_f32 v255, s105, v0, v1 :: v_dual_fma_f32 v7, s1, v0, -abs(v8)285// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: ABS not allowed in VOPD3 instructions286// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, s105, v0, v1 :: v_dual_fma_f32 v7, s1, v0, -abs(v8)287// GFX12-NEXT:{{^}} ^288 289v_dual_mul_f64 v[6:7], -|v[2:3]|, v[4:5] :: v_dual_fma_f32 v255, -s105, v2, v1290// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: ABS not allowed in VOPD3 instructions291// GFX12-NEXT:{{^}}v_dual_mul_f64 v[6:7], -|v[2:3]|, v[4:5] :: v_dual_fma_f32 v255, -s105, v2, v1292// GFX12-NEXT:{{^}} ^293 294//===----------------------------------------------------------------------===//295// No modifiers on non-fp part of an instruction296//===----------------------------------------------------------------------===//297v_dual_fma_f32 v255, -s105, v0, v1 :: v_dual_lshrrev_b32 v7, -s1, v0298// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction299// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, -s105, v0, v1 :: v_dual_lshrrev_b32 v7, -s1, v0300// GFX12-NEXT:{{^}} ^301 302v_dual_fma_f32 v255, -s105, v0, v1 :: v_dual_max_i32 v7, s1, -v0303// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction304// GFX12-NEXT:{{^}}v_dual_fma_f32 v255, -s105, v0, v1 :: v_dual_max_i32 v7, s1, -v0305// GFX12-NEXT:{{^}} ^306 307v_dual_add_nc_u32 v7, -s1, v0 :: v_dual_fma_f32 v255, -s105, v0, v1308// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand309// GFX12-NEXT:{{^}}v_dual_add_nc_u32 v7, -s1, v0 :: v_dual_fma_f32 v255, -s105, v0, v1310// GFX12-NEXT:{{^}} ^311 312v_dual_sub_nc_u32 v7, s1, -v0 :: v_dual_fma_f32 v255, -s105, v0, v1313// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand314// GFX12-NEXT:{{^}}v_dual_sub_nc_u32 v7, s1, -v0 :: v_dual_fma_f32 v255, -s105, v0, v1315// GFX12-NEXT:{{^}} ^316 317v_dual_cndmask_b32 v28, sext(v15), v15, s46 :: v_dual_cndmask_b32 v29, v13, -v13, s46318// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand319// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v28, sext(v15), v15, s46 :: v_dual_cndmask_b32 v29, v13, -v13, s46320// GFX12-NEXT:{{^}} ^321 322 323v_dual_cndmask_b32 v28, -v15, v15, s46 :: v_dual_cndmask_b32 v29, sext(v13), -v13, s46324// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand325// GFX12-NEXT:{{^}}v_dual_cndmask_b32 v28, -v15, v15, s46 :: v_dual_cndmask_b32 v29, sext(v13), -v13, s46326// GFX12-NEXT:{{^}} ^327