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1// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s2// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI9,VI %s3// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GCN,VI9,GFX9 %s4// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s5// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX11 %s6 7// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s8// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s9// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefix=NOGFX9 --implicit-check-not=error: %s10// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=NOGFX10 --implicit-check-not=error: %s11// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=NOGFX11 --implicit-check-not=error: %s12 13//===----------------------------------------------------------------------===//14// Instructions15//===----------------------------------------------------------------------===//16 17s_movk_i32 s2, 0x618// GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0]19 20s_cmovk_i32 s2, 0x621// SICI: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]22// VI9: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb0]23// GFX10: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]24// GFX11: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]25 26s_cmpk_eq_i32 s2, 0x627// SICI: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]28// VI9: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]29// GFX10: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]30// GFX11: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]31 32s_cmpk_lg_i32 s2, 0x633// SICI: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]34// VI9: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]35// GFX10: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]36// GFX11: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]37 38s_cmpk_gt_i32 s2, 0x639// SICI: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]40// VI9: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]41// GFX10: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]42// GFX11: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]43 44s_cmpk_ge_i32 s2, 0x645// SICI: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]46// VI9: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]47// GFX10: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]48// GFX11: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]49 50s_cmpk_lt_i32 s2, 0x651// SICI: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]52// VI9: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]53// GFX10: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]54// GFX11: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]55 56s_cmpk_le_i32 s2, 0x657// SICI: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]58// VI9: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]59// GFX10: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]60// GFX11: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]61 62s_cmpk_eq_u32 s2, 0x663// SICI: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]64// VI9: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]65// GFX10: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]66// GFX11: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]67 68s_cmpk_lg_u32 s2, 0x669// SICI: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]70// VI9: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]71// GFX10: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]72// GFX11: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]73 74s_cmpk_gt_u32 s2, 0x675// SICI: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]76// VI9: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]77// GFX10: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]78// GFX11: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]79 80s_cmpk_ge_u32 s2, 0x681// SICI: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]82// VI9: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]83// GFX10: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]84// GFX11: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]85 86s_cmpk_lt_u32 s2, 0x687// SICI: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]88// VI9: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]89// GFX10: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]90// GFX11: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]91 92s_cmpk_le_u32 s2, 0x693// SICI: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]94// VI9: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]95// GFX10: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]96// GFX11: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]97 98s_cmpk_le_u32 s2, 0xFFFF99// SICI: s_cmpk_le_u32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb7]100// VI9: s_cmpk_le_u32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb6]101// GFX10: s_cmpk_le_u32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb7]102// GFX11: s_cmpk_le_u32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb7]103 104s_addk_i32 s2, 0x6105// SICI: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]106// VI9: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]107// GFX10: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]108// GFX11: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]109 110s_mulk_i32 s2, 0x6111// SICI: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8]112// VI9: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]113// GFX10: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8]114// GFX11: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8]115 116s_mulk_i32 s2, -1117// SICI: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]118// VI9: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]119// GFX10: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]120// GFX11: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]121 122s_mulk_i32 s2, 0xFFFF123// SICI: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]124// VI9: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]125// GFX10: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]126// GFX11: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]127 128s_cbranch_i_fork s[2:3], 0x6129// SICI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x82,0xb8]130// VI9: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]131// NOGFX10: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU132// NOGFX11: :[[@LINE-4]]:{{[0-9]+}}: error: instruction not supported on this GPU133 134//===----------------------------------------------------------------------===//135// getreg/setreg and hwreg macro136//===----------------------------------------------------------------------===//137 138// raw number mapped to known HW register139s_getreg_b32 s2, 0x6140// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]141// VI9: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]142// GFX10: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]143// GFX11: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]144 145// HW register identifier, non-default offset/width146s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31)147// SICI: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x02,0xb9]148// VI9: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x82,0xb8]149// GFX10: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x02,0xb9]150// GFX11: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x82,0xb8]151 152// HW register code of unknown HW register, non-default offset/width153s_getreg_b32 s2, hwreg(51, 1, 31)154// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]155// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]156// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]157// GFX11: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]158 159s_getreg_b32 s2, {id: 51, offset: 1, size: 31}160// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]161// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]162// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]163// GFX11: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]164 165// HW register code of unknown HW register, default offset/width166s_getreg_b32 s2, hwreg(51)167// SICI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9]168// VI9: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]169// GFX10: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9]170// GFX11: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]171 172// Structured form using default values.173s_getreg_b32 s2, {id: 51}174// SICI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9]175// VI9: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]176// GFX10: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9]177// GFX11: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]178 179// Fields may come in any order.180s_getreg_b32 s2, {size: 32, id: 51}181// SICI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9]182// VI9: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]183// GFX10: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9]184// GFX11: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]185 186// Empty field lists are allowed.187s_getreg_b32 s2, {}188// SICI: s_getreg_b32 s2, hwreg(0) ; encoding: [0x00,0xf8,0x02,0xb9]189// VI9: s_getreg_b32 s2, hwreg(0) ; encoding: [0x00,0xf8,0x82,0xb8]190// GFX10: s_getreg_b32 s2, hwreg(0) ; encoding: [0x00,0xf8,0x02,0xb9]191// GFX11: s_getreg_b32 s2, hwreg(0) ; encoding: [0x00,0xf8,0x82,0xb8]192 193// HW register code of unknown HW register, valid symbolic name range but no name available194s_getreg_b32 s2, hwreg(10)195// SICI: s_getreg_b32 s2, hwreg(10) ; encoding: [0x0a,0xf8,0x02,0xb9]196// VI9: s_getreg_b32 s2, hwreg(10) ; encoding: [0x0a,0xf8,0x82,0xb8]197// GFX10: s_getreg_b32 s2, hwreg(10) ; encoding: [0x0a,0xf8,0x02,0xb9]198// GFX11: s_getreg_b32 s2, hwreg(10) ; encoding: [0x0a,0xf8,0x82,0xb8]199 200// HW_REG_SH_MEM_BASES valid starting from GFX9201s_getreg_b32 s2, hwreg(15)202// SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9]203// VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8]204// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]205// GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]206// GFX11: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]207 208s_getreg_b32 s2, hwreg(16)209// SICI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9]210// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]211// GFX11: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]212// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]213// VI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]214 215s_getreg_b32 s2, hwreg(17)216// SICI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9]217// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]218// GFX11: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]219// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]220// VI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]221 222s_getreg_b32 s2, hwreg(18)223// SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9]224// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]225// GFX11: s_getreg_b32 s2, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO) ; encoding: [0x12,0xf8,0x82,0xb8]226// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]227// VI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]228 229s_getreg_b32 s2, hwreg(19)230// SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9]231// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]232// GFX11: s_getreg_b32 s2, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI) ; encoding: [0x13,0xf8,0x82,0xb8]233// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]234// VI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]235 236// GFX10+ registers237s_getreg_b32 s2, hwreg(20)238// SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9]239// VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8]240// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]241// GFX11: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x82,0xb8]242 243s_getreg_b32 s2, hwreg(21)244// SICI: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x02,0xb9]245// VI9: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x82,0xb8]246// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9]247// GFX11: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x82,0xb8]248 249s_getreg_b32 s2, hwreg(22)250// SICI: s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x02,0xb9]251// VI9: s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x82,0xb8]252// GFX10: s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9]253// GFX11: s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x82,0xb8]254 255s_getreg_b32 s2, hwreg(23)256// SICI: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x02,0xb9]257// VI9: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x82,0xb8]258// GFX10: s_getreg_b32 s2, hwreg(HW_REG_HW_ID1) ; encoding: [0x17,0xf8,0x02,0xb9]259// GFX11: s_getreg_b32 s2, hwreg(HW_REG_HW_ID1) ; encoding: [0x17,0xf8,0x82,0xb8]260 261s_getreg_b32 s2, hwreg(24)262// SICI: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x02,0xb9]263// VI9: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x82,0xb8]264// GFX10: s_getreg_b32 s2, hwreg(HW_REG_HW_ID2) ; encoding: [0x18,0xf8,0x02,0xb9]265// GFX11: s_getreg_b32 s2, hwreg(HW_REG_HW_ID2) ; encoding: [0x18,0xf8,0x82,0xb8]266 267s_getreg_b32 s2, hwreg(25)268// SICI: s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x02,0xb9]269// VI9: s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x82,0xb8]270// GFX10: s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9]271// GFX11: s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x82,0xb8]272 273// raw number mapped to known HW register274s_setreg_b32 0x6, s2275// SICI: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x82,0xb9]276// VI9: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]277// GFX10: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x82,0xb9]278// GFX11: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]279 280// raw number mapped to unknown HW register281s_setreg_b32 0x33, s2282// SICI: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x82,0xb9]283// VI9: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x02,0xb9]284// GFX10: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x82,0xb9]285// GFX11: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x02,0xb9]286 287// raw number mapped to known HW register, default offset/width288s_setreg_b32 0xf803, s2289// SICI: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x82,0xb9]290// VI9: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x02,0xb9]291// GFX10: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x82,0xb9]292// GFX11: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x02,0xb9]293 294// HW register identifier, default offset/width implied295s_setreg_b32 hwreg(HW_REG_HW_ID), s2296// SICI: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x82,0xb9]297// VI9: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x02,0xb9]298// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2 ; encoding: [0x17,0xf8,0x82,0xb9]299// NOGFX11: :[[@LINE-4]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU300 301s_setreg_b32 hwreg(HW_REG_HW_ID1), s2302// NOSICIVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU303// NOGFX9: :[[@LINE-2]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU304// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2 ; encoding: [0x17,0xf8,0x82,0xb9]305// GFX11: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2 ; encoding: [0x17,0xf8,0x02,0xb9]306 307s_setreg_b32 hwreg(HW_REG_HW_ID2), s2308// NOSICIVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU309// NOGFX9: :[[@LINE-2]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU310// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID2), s2 ; encoding: [0x18,0xf8,0x82,0xb9]311// GFX11: s_setreg_b32 hwreg(HW_REG_HW_ID2), s2 ; encoding: [0x18,0xf8,0x02,0xb9]312 313// HW register identifier, non-default offset/width314s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2315// SICI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]316// VI9: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x02,0xb9]317// GFX10: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]318// GFX11: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x02,0xb9]319 320// HW register code of unknown HW register, valid symbolic name range but no name available321s_setreg_b32 hwreg(10), s2322// SICI: s_setreg_b32 hwreg(10), s2 ; encoding: [0x0a,0xf8,0x82,0xb9]323// VI9: s_setreg_b32 hwreg(10), s2 ; encoding: [0x0a,0xf8,0x02,0xb9]324// GFX10: s_setreg_b32 hwreg(10), s2 ; encoding: [0x0a,0xf8,0x82,0xb9]325// GFX11: s_setreg_b32 hwreg(10), s2 ; encoding: [0x0a,0xf8,0x02,0xb9]326 327// HW_REG_SH_MEM_BASES valid starting from GFX9328s_setreg_b32 hwreg(15), s2329// SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]330// VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]331// GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]332// GFX10: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]333// GFX11: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]334 335s_setreg_b32 hwreg(16), s2336// SICI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x82,0xb9]337// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9]338// GFX11: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]339// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x02,0xb9]340// VI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]341 342s_setreg_b32 hwreg(17), s2343// SICI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x82,0xb9]344// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9]345// GFX11: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]346// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x02,0xb9]347// VI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]348 349s_setreg_b32 hwreg(18), s2350// SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9]351// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9]352// GFX11: s_setreg_b32 hwreg(HW_REG_PERF_SNAPSHOT_PC_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9]353// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9]354// VI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]355 356s_setreg_b32 hwreg(19), s2357// SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9]358// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9]359// GFX11: s_setreg_b32 hwreg(HW_REG_PERF_SNAPSHOT_PC_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9]360// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9]361// VI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]362 363// GFX10+ registers364s_setreg_b32 hwreg(20), s2365// SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9]366// VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9]367// GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9]368// GFX11: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x02,0xb9]369 370s_setreg_b32 hwreg(21), s2371// SICI: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x82,0xb9]372// VI9: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x02,0xb9]373// GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s2 ; encoding: [0x15,0xf8,0x82,0xb9]374// GFX11: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s2 ; encoding: [0x15,0xf8,0x02,0xb9]375 376s_setreg_b32 hwreg(22), s2377// SICI: s_setreg_b32 hwreg(22), s2 ; encoding: [0x16,0xf8,0x82,0xb9]378// VI9: s_setreg_b32 hwreg(22), s2 ; encoding: [0x16,0xf8,0x02,0xb9]379// GFX10: s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s2 ; encoding: [0x16,0xf8,0x82,0xb9]380// GFX11: s_setreg_b32 hwreg(22), s2 ; encoding: [0x16,0xf8,0x02,0xb9]381 382s_setreg_b32 hwreg(23), s2383// SICI: s_setreg_b32 hwreg(23), s2 ; encoding: [0x17,0xf8,0x82,0xb9]384// VI9: s_setreg_b32 hwreg(23), s2 ; encoding: [0x17,0xf8,0x02,0xb9]385// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2 ; encoding: [0x17,0xf8,0x82,0xb9]386// GFX11: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2 ; encoding: [0x17,0xf8,0x02,0xb9]387 388s_setreg_b32 hwreg(24), s2389// SICI: s_setreg_b32 hwreg(24), s2 ; encoding: [0x18,0xf8,0x82,0xb9]390// VI9: s_setreg_b32 hwreg(24), s2 ; encoding: [0x18,0xf8,0x02,0xb9]391// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID2), s2 ; encoding: [0x18,0xf8,0x82,0xb9]392// GFX11: s_setreg_b32 hwreg(HW_REG_HW_ID2), s2 ; encoding: [0x18,0xf8,0x02,0xb9]393 394s_setreg_b32 hwreg(25), s2395// SICI: s_setreg_b32 hwreg(25), s2 ; encoding: [0x19,0xf8,0x82,0xb9]396// VI9: s_setreg_b32 hwreg(25), s2 ; encoding: [0x19,0xf8,0x02,0xb9]397// GFX10: s_setreg_b32 hwreg(HW_REG_POPS_PACKER), s2 ; encoding: [0x19,0xf8,0x82,0xb9]398// GFX11: s_setreg_b32 hwreg(25), s2 ; encoding: [0x19,0xf8,0x02,0xb9]399 400// HW register code, non-default offset/width401s_setreg_b32 hwreg(5, 1, 31), s2402// SICI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]403// VI9: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x02,0xb9]404// GFX10: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]405// GFX11: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x02,0xb9]406 407// raw number mapped to known HW register408s_setreg_imm32_b32 0x6, 0xff409// SICI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]410// VI9: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]411// GFX10: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]412// GFX11: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xb9,0xff,0x00,0x00,0x00]413 414// HW register identifier, non-default offset/width415s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff416// SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]417// VI9: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]418// GFX10: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]419// GFX11: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xb9,0xff,0x00,0x00,0x00]420 421//===----------------------------------------------------------------------===//422// expressions and hwreg macro423//===----------------------------------------------------------------------===//424 425hwreg=6426s_getreg_b32 s2, hwreg427// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]428// VI9: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]429// GFX10: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]430// GFX11: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]431 432x=5433s_getreg_b32 s2, x+1434// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]435// VI9: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]436// GFX10: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]437// GFX11: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]438 439x=5440s_getreg_b32 s2, 1+x441// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]442// VI9: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]443// GFX10: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]444// GFX11: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]445 446reg=50447offset=2448width=30449s_getreg_b32 s2, hwreg(reg + 1, offset - 1, width + 1)450// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]451// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]452// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]453// GFX11: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]454 455s_getreg_b32 s2, {id: reg + 1, offset: offset - 1, size: width + 1}456// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]457// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]458// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]459// GFX11: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]460 461s_getreg_b32 s2, hwreg(1 + reg, -1 + offset, 1 + width)462// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]463// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]464// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]465// GFX11: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]466 467s_getreg_b32 s2, {id: 1 + reg, offset: -1 + offset, size: 1 + width}468// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]469// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]470// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]471// GFX11: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]472 473//===----------------------------------------------------------------------===//474// Instructions475//===----------------------------------------------------------------------===//476 477s_endpgm_ordered_ps_done478// GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]479// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU480// GFX10: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]481// GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]482 483s_call_b64 null, 12609484// GFX10: s_call_b64 null, 12609 ; encoding: [0x41,0x31,0x7d,0xbb]485// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU486// NOGFX9: :[[@LINE-3]]:{{[0-9]+}}: error: 'null' operand is not supported on this GPU487// GFX11: s_call_b64 null, 12609 ; encoding: [0x41,0x31,0x7c,0xba]488 489s_call_b64 s[12:13], 12609490// GFX9: s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x8c,0xba]491// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU492// GFX10: s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x0c,0xbb]493// GFX11: s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x0c,0xba]494 495s_call_b64 s[100:101], 12609496// GFX9: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0xe4,0xba]497// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU498// GFX10: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0x64,0xbb]499// GFX11: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0x64,0xba]500 501s_call_b64 s[10:11], 49617502// GFX9: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x8a,0xba]503// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU504// GFX10: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x0a,0xbb]505// GFX11: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x0a,0xba]506 507offset = 4508s_call_b64 s[0:1], offset + 4509// GFX9: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x80,0xba]510// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU511// GFX10: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x00,0xbb]512// GFX11: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x00,0xba]513 514offset = 4515s_call_b64 s[0:1], 4 + offset516// GFX9: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x80,0xba]517// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU518// GFX10: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x00,0xbb]519// GFX11: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x00,0xba]520