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1// RUN: not llvm-mc -triple armv8a -show-encoding -mattr=+i8mm < %s 2>&1 | FileCheck %s2// RUN: not llvm-mc -triple thumbv8a -show-encoding -mattr=+i8mm < %s 2>&1 | FileCheck %s3 4 5// VSMMLA, VUMMLA, VUSMMLA6 7// Data type specifier must match instruction8 9vsmmla.u8 q0, q1, q210// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction11// CHECK-NEXT: vsmmla.u8 q0, q1, q212// CHECK-NEXT: {{^ \^}}13 14vummla.s8 q0, q1, q215// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction16// CHECK-NEXT: vummla.s8 q0, q1, q217// CHECK-NEXT: {{^ \^}}18 19vusmmla.u8 q0, q1, q220// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction21// CHECK-NEXT: vusmmla.u8 q0, q1, q222// CHECK-NEXT: {{^ \^}}23 24 25// Incorrect register type26 27vsmmla.s8 d0, q1, q228// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [q0, q15]29// CHECK-NEXT: vsmmla.s8 d0, q1, q230// CHECK-NEXT: {{^ \^}}31 32vummla.u8 q0, d1, q233// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [q0, q15]34// CHECK-NEXT: vummla.u8 q0, d1, q235// CHECK-NEXT: {{^ \^}}36 37vusmmla.s8 q0, q1, d238// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [q0, q15]39// CHECK-NEXT: vusmmla.s8 q0, q1, d240// CHECK-NEXT: {{^ \^}}41 42 43// VUSDOT (vector)44 45// Data type specifier must match instruction46 47vusdot.u8 q0, q1, q248// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction49// CHECK-NEXT: vusdot.u8 q0, q1, q250// CHECK-NEXT: {{^ \^}}51 52// Mis-matched register types53 54vusdot.s8 q0, d1, d255// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d31]56vusdot.s8 d0, q1, d257// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d31]58vusdot.s8 d0, d1, q259// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d31]60 61 62// VUSDOT, VSUDOT (by scalar)63 64// Data type specifier must match instruction65 66vusdot.u8 d0, d1, d2[0]67// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction68// CHECK-NEXT: vusdot.u8 d0, d1, d2[0]69// CHECK-NEXT: {{^ \^}}70 71vsudot.s8 d0, d1, d2[0]72// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction73// CHECK-NEXT: vsudot.s8 d0, d1, d2[0]74// CHECK-NEXT: {{^ \^}}75 76// Incorrect register types77 78vusdot.s8 q0, d1, d2[0]79// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:80// CHECK-NEXT: vusdot.s8 q0, d1, d2[0]81// CHECK: [[@LINE-3]]:{{[0-9]+}}: note: operand must be a register in range [d0, d31]82// CHECK-NEXT: vusdot.s8 q0, d1, d2[0]83// CHECK-NEXT: {{^ \^}}84// CHECK: [[@LINE-6]]:{{[0-9]+}}: note: operand must be a register in range [q0, q15]85// CHECK-NEXT: vusdot.s8 q0, d1, d2[0]86// CHECK-NEXT: {{^ \^}}87 88vusdot.s8 d0, q1, d2[0]89// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:90// CHECK-NEXT: vusdot.s8 d0, q1, d2[0]91// CHECK: [[@LINE-3]]:{{[0-9]+}}: note: operand must be a register in range [d0, d31]92// CHECK-NEXT: vusdot.s8 d0, q1, d2[0]93// CHECK-NEXT: {{^ \^}}94// CHECK: [[@LINE-6]]:{{[0-9]+}}: note: operand must be a register in range [q0, q15]95// CHECK-NEXT: vusdot.s8 d0, q1, d2[0]96// CHECK-NEXT: {{^ \^}}97 98vusdot.s8 q0, q1, q2[0]99// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:100// CHECK-NEXT: vusdot.s8 q0, q1, q2[0]101// CHECK: [[@LINE-3]]:{{[0-9]+}}: note: operand must be a register in range [d0, d15]102// CHECK-NEXT: vusdot.s8 q0, q1, q2[0]103// CHECK-NEXT: {{^ \^}}104// CHECK: [[@LINE-6]]:{{[0-9]+}}: note: too many operands for instruction105// CHECK-NEXT: vusdot.s8 q0, q1, q2[0]106// CHECK-NEXT: {{^ \^}}107 108// Out of range lane index109 110vusdot.s8 d0, d1, d2[2]111// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction112vsudot.u8 q0, q1, d2[2]113// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction114