211 lines · plain
1//RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aTHUMB2//RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s3//RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aARM4//RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s5 6//RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V87//RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V88 9 10 .text11//CHECK-V8THUMB: .text12 13 vqrdmlah.i8 q0, q1, q214 vqrdmlah.u16 d0, d1, d215 vqrdmlsh.f32 q3, q4, q516 vqrdmlsh.f64 d3, d5, d517 18//CHECK-ERROR: error: invalid operand for instruction19//CHECK-ERROR: vqrdmlah.i8 q0, q1, q220//CHECK-ERROR: ^21//CHECK-ERROR: error: invalid operand for instruction22//CHECK-ERROR: vqrdmlah.u16 d0, d1, d223//CHECK-ERROR: ^24//CHECK-ERROR: error: invalid operand for instruction25//CHECK-ERROR: vqrdmlsh.f32 q3, q4, q526//CHECK-ERROR: ^27//CHECK-ERROR: error: invalid operand for instruction28//CHECK-ERROR: vqrdmlsh.f64 d3, d5, d529//CHECK-ERROR: ^30//CHECK-V8: error: invalid instruction31//CHECK-V8: vqrdmlah.i8 q0, q1, q232//CHECK-V8: ^33//CHECK-V8: error: invalid instruction34//CHECK-V8: vqrdmlah.u16 d0, d1, d235//CHECK-V8: ^36//CHECK-V8: error: invalid instruction37//CHECK-V8: vqrdmlsh.f32 q3, q4, q538//CHECK-V8: ^39//CHECK-V8: error: invalid instruction40//CHECK-V8: vqrdmlsh.f64 d3, d5, d541//CHECK-V8: ^42 43 vqrdmlah.s16 d0, d1, d244//CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x12,0x0b,0x11,0xf3]45//CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0b]46//CHECK-V8: error: instruction requires: armv8.1a47//CHECK-V8: vqrdmlah.s16 d0, d1, d248//CHECK-V8: ^49 50 vqrdmlah.s32 d0, d1, d251//CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x12,0x0b,0x21,0xf3]52//CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0b]53//CHECK-V8: error: instruction requires: armv8.1a54//CHECK-V8: vqrdmlah.s32 d0, d1, d255//CHECK-V8: ^56 57 vqrdmlah.s16 q0, q1, q258//CHECK-V81aARM: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x54,0x0b,0x12,0xf3]59//CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0b]60//CHECK-V8: error: instruction requires: armv8.1a61//CHECK-V8: vqrdmlah.s16 q0, q1, q262//CHECK-V8: ^63 64 vqrdmlah.s32 q2, q3, q065//CHECK-V81aARM: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x50,0x4b,0x26,0xf3]66//CHECK-V81aTHUMB: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x26,0xff,0x50,0x4b]67//CHECK-V8: error: instruction requires: armv8.1a68//CHECK-V8: vqrdmlah.s32 q2, q3, q069//CHECK-V8: ^70 71 72 vqrdmlsh.s16 d7, d6, d573//CHECK-V81aARM: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x15,0x7c,0x16,0xf3]74//CHECK-V81aTHUMB: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x16,0xff,0x15,0x7c]75//CHECK-V8: error: instruction requires: armv8.1a76//CHECK-V8: vqrdmlsh.s16 d7, d6, d577//CHECK-V8: ^78 79 vqrdmlsh.s32 d0, d1, d280//CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x12,0x0c,0x21,0xf3]81//CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0c]82//CHECK-V8: error: instruction requires: armv8.1a83//CHECK-V8: vqrdmlsh.s32 d0, d1, d284//CHECK-V8: ^85 86 vqrdmlsh.s16 q0, q1, q287//CHECK-V81aARM: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x54,0x0c,0x12,0xf3]88//CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0c]89//CHECK-V8: error: instruction requires: armv8.1a90//CHECK-V8: vqrdmlsh.s16 q0, q1, q291//CHECK-V8: ^92 93 vqrdmlsh.s32 q3, q4, q594//CHECK-V81aARM: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x5a,0x6c,0x28,0xf3]95//CHECK-V81aTHUMB: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x28,0xff,0x5a,0x6c]96//CHECK-V8: error: instruction requires: armv8.1a97//CHECK-V8: vqrdmlsh.s32 q3, q4, q598//CHECK-V8: ^99 100 101 vqrdmlah.i8 q0, q1, d9[0]102 vqrdmlah.s32 q0, q1, d9[7]103 vqrdmlah.u16 d0, d1, d2[3]104 vqrdmlsh.f32 q3, q4, d5[1]105 vqrdmlsh.f64 d3, d5, d5[0]106 107//CHECK-ERROR: error: invalid operand for instruction108//CHECK-ERROR: vqrdmlah.i8 q0, q1, d9[0]109//CHECK-ERROR: ^110//CHECK-ERROR: error: invalid operand for instruction111//CHECK-ERROR: vqrdmlah.s32 q0, q1, d9[7]112//CHECK-ERROR: ^113//CHECK-ERROR: error: invalid operand for instruction114//CHECK-ERROR: vqrdmlah.u16 d0, d1, d2[3]115//CHECK-ERROR: ^116//CHECK-ERROR: error: invalid operand for instruction117//CHECK-ERROR: vqrdmlsh.f32 q3, q4, d5[1]118//CHECK-ERROR: ^119//CHECK-ERROR: error: invalid operand for instruction120//CHECK-ERROR: vqrdmlsh.f64 d3, d5, d5[0]121//CHECK-ERROR: ^122 123 vqrdmlah.s16 d0, d1, d2[0]124//CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x42,0x0e,0x91,0xf2]125//CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0e]126//CHECK-V8: error: instruction requires: armv8.1a127//CHECK-V8: vqrdmlah.s16 d0, d1, d2[0]128//CHECK-V8: ^129 130 vqrdmlah.s32 d0, d1, d2[0]131//CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0x42,0x0e,0xa1,0xf2]132//CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0e]133//CHECK-V8: error: instruction requires: armv8.1a134//CHECK-V8: vqrdmlah.s32 d0, d1, d2[0]135//CHECK-V8: ^136 137 vqrdmlah.s16 q0, q1, d2[0]138//CHECK-V81aARM: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x42,0x0e,0x92,0xf3]139//CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0e]140//CHECK-V8: error: instruction requires: armv8.1a141//CHECK-V8: vqrdmlah.s16 q0, q1, d2[0]142//CHECK-V8: ^143 144 vqrdmlah.s32 q0, q1, d2[0]145//CHECK-V81aARM: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0x42,0x0e,0xa2,0xf3]146//CHECK-V81aTHUMB: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0e]147//CHECK-V8: error: instruction requires: armv8.1a148//CHECK-V8: vqrdmlah.s32 q0, q1, d2[0]149//CHECK-V8: ^150 151 152 vqrdmlsh.s16 d0, d1, d2[0]153//CHECK-V81aARM: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x42,0x0f,0x91,0xf2]154//CHECK-V81aTHUMB: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0f]155//CHECK-V8: error: instruction requires: armv8.1a156//CHECK-V8: vqrdmlsh.s16 d0, d1, d2[0]157//CHECK-V8: ^158 159 vqrdmlsh.s32 d0, d1, d2[0]160//CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0x42,0x0f,0xa1,0xf2]161//CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0f]162//CHECK-V8: error: instruction requires: armv8.1a163//CHECK-V8: vqrdmlsh.s32 d0, d1, d2[0]164//CHECK-V8: ^165 166 vqrdmlsh.s16 q0, q1, d2[0]167//CHECK-V81aARM: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x42,0x0f,0x92,0xf3]168//CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0f]169//CHECK-V8: error: instruction requires: armv8.1a170//CHECK-V8: vqrdmlsh.s16 q0, q1, d2[0]171//CHECK-V8: ^172 173 vqrdmlsh.s32 q0, q1, d2[0]174//CHECK-V81aARM: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0x42,0x0f,0xa2,0xf3]175//CHECK-V81aTHUMB: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0f]176//CHECK-V8: error: instruction requires: armv8.1a177//CHECK-V8: vqrdmlsh.s32 q0, q1, d2[0]178//CHECK-V8: ^179 180 setpan #0181//CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6]182//CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1]183//CHECK-V8: instruction requires: armv8.1a184//CHECK-V8: setpan #0185//CHECK-V8: ^186 187 setpan #1188//CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6]189//CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1]190//CHECK-V8: instruction requires: armv8.1a191//CHECK-V8: setpan #1192//CHECK-V8: ^193 setpan194 setpan #-1195 setpan #2196//CHECK-ERROR: error: too few operands for instruction197//CHECK-ERROR: setpan198//CHECK-ERROR: ^199//CHECK-ERROR: error: operand must be an immediate in the range [0,1]200//CHECK-ERROR: setpan #-1201//CHECK-ERROR: ^202//CHECK-ERROR: error: operand must be an immediate in the range [0,1]203//CHECK-ERROR: setpan #2204//CHECK-ERROR: ^205 206 it eq207 setpaneq #0208//CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified209//CHECK-THUMB-ERROR: setpaneq #0210//CHECK-THUMB-ERROR: ^211