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1@ New ARMv8 T32 encodings2 3@ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V84@ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V75 6@ HLT (in ARMv8 only)7        hlt  #08        hlt  #639@ CHECK-V8: hlt  #0                       @ encoding: [0x80,0xba]10@ CHECK-V8: hlt  #63                      @ encoding: [0xbf,0xba]11@ CHECK-V7: error: instruction requires: armv812@ CHECK-V7: error: instruction requires: armv813 14@ In IT block15        it pl16        hlt #2417 18@ CHECK-V8: it pl                         @ encoding: [0x58,0xbf]19@ CHECK-V8: hlt #24                       @ encoding: [0x98,0xba]20@ CHECK-V7: error: instruction requires: armv821 22@ Can accept AL condition code (in ARMv8 only)23        hltal #2424@ CHECK-V8: hlt #24                       @ encoding: [0x98,0xba]25@ CHECK-V7: error: instruction requires: armv826 27@ Can accept SP as rGPR (in ARMv8 only)28        sbc.w r6, r3, sp, asr #1629        and.w r6, r3, sp, asr #1630        and sp, r0, #031@ CHECK-V8: sbc.w r6, r3, sp, asr #16     @ encoding: [0x63,0xeb,0x2d,0x46]32@ CHECK-V8: and.w r6, r3, sp, asr #16     @ encoding: [0x03,0xea,0x2d,0x46]33@ CHECK-V8: and   sp, r0, #0              @ encoding: [0x00,0xf0,0x00,0x0d]34@ CHECK-V7: error: invalid instruction, any one of the following would fix this:35@ CHECK-V7-NEXT: sbc.w r6, r3, sp, asr #1636@ CHECK-V7: note: instruction variant requires ARMv8 or later37@ CHECK-V7: note: operand must be a register in range [r0, r12] or r1438@ CHECK-V7: error: invalid instruction, any one of the following would fix this:39@ CHECK-V7-NEXT: and.w r6, r3, sp, asr #1640@ CHECK-V7: note: invalid operand for instruction41@ CHECK-V7: note: instruction variant requires ARMv8 or later42@ CHECK-V7: note: operand must be a register in range [r0, r12] or r1443@ CHECK-V7: error: invalid instruction, any one of the following would fix this:44@ CHECK-V7-NEXT: and sp, r0, #045@ CHECK-V7: note: operand must be a register in range [r0, r12] or r1446@ CHECK-V7: note: invalid operand for instruction47 48@ DCPS{1,2,3} (in ARMv8 only)49        dcps150        dcps251        dcps352@ CHECK-V8: dcps1                         @ encoding: [0x8f,0xf7,0x01,0x80]53@ CHECK-V8: dcps2                         @ encoding: [0x8f,0xf7,0x02,0x80]54@ CHECK-V8: dcps3                         @ encoding: [0x8f,0xf7,0x03,0x80]55@ CHECK-V7: error: instruction requires: armv856@ CHECK-V7: error: instruction requires: armv857@ CHECK-V7: error: instruction requires: armv858 59@------------------------------------------------------------------------------60@ DMB (ARMv8-only barriers)61@------------------------------------------------------------------------------62        dmb ishld63        dmb oshld64        dmb nshld65        dmb ld66 67@ CHECK-V8: dmb ishld @ encoding: [0xbf,0xf3,0x59,0x8f]68@ CHECK-V8: dmb oshld @ encoding: [0xbf,0xf3,0x51,0x8f]69@ CHECK-V8: dmb nshld @ encoding: [0xbf,0xf3,0x55,0x8f]70@ CHECK-V8: dmb ld @ encoding: [0xbf,0xf3,0x5d,0x8f]71@ CHECK-V7: error: invalid operand for instruction72@ CHECK-V7: error: invalid operand for instruction73@ CHECK-V7: error: invalid operand for instruction74@ CHECK-V7: error: invalid operand for instruction75 76@------------------------------------------------------------------------------77@ DSB (ARMv8-only barriers)78@------------------------------------------------------------------------------79        dsb ishld80        dsb oshld81        dsb nshld82        dsb ld83 84@ CHECK-V8: dsb ishld @ encoding: [0xbf,0xf3,0x49,0x8f]85@ CHECK-V8: dsb oshld @ encoding: [0xbf,0xf3,0x41,0x8f]86@ CHECK-V8: dsb nshld @ encoding: [0xbf,0xf3,0x45,0x8f]87@ CHECK-V8: dsb ld @ encoding: [0xbf,0xf3,0x4d,0x8f]88@ CHECK-V7: error: invalid operand for instruction89@ CHECK-V7: error: invalid operand for instruction90@ CHECK-V7: error: invalid operand for instruction91@ CHECK-V7: error: invalid operand for instruction92 93@------------------------------------------------------------------------------94@ SEVL (in ARMv8 only)95@------------------------------------------------------------------------------96        sevl97        sevl.w98        it ge99        sevlge100 101@ CHECK-V8: sevl @ encoding: [0x50,0xbf]102@ CHECK-V8: sevl.w @ encoding: [0xaf,0xf3,0x05,0x80]103@ CHECK-V8: it ge @ encoding: [0xa8,0xbf]104@ CHECK-V8: sevlge @ encoding: [0x50,0xbf]105@ CHECK-V7: error: instruction requires: armv8106@ CHECK-V7: error: instruction requires: armv8107@ CHECK-V7: error:108@ CHECK-V7: error: instruction requires: armv8109