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1@ RUN: llvm-mc -triple arm-none-eabi -filetype asm %s 2>%t | FileCheck %s2@ RUN: FileCheck %s <%t --check-prefix=STDERR3 4@ Start in arm mode5 .arm6@ CHECK: .code 327 8@ In ARM mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in ARM mode)9 .arch armv7-a10@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:11@ CHECK-NOT: .code12@ CHECK: .arch armv7-a13@ CHECK-NOT: .code14 15@ In ARM mode, switch to an arch which has Thumb only, expect warning and .code 16 directive16 .arch armv6-m17@ STDERR: [[@LINE-1]]:{{[0-9]+}}: warning: new target does not support arm mode, switching to thumb mode18@ CHECK: .code 1619@ CHECK: .arch armv6-m20 21@ In Thumb mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in Thumb mode)22 .arch armv7-a23@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:24@ CHECK-NOT: .code25@ CHECK: .arch armv7-a26@ CHECK-NOT: .code27 28@ In Thumb mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in Thumb mode)29 .cpu cortex-a830@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:31@ CHECK-NOT: .code32@ CHECK: .cpu cortex-a833@ CHECK-NOT: .code34 35@ Switch to ARM mode36 .arm37@ CHECK: .code 3238@ CHECK: .p2align 239 40@ In ARM mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in ARM mode)41 .cpu cortex-a842@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:43@ CHECK-NOT: .code44@ CHECK: .cpu cortex-a845@ CHECK-NOT: .code46 47@ In ARM mode, switch to a CPU which has Thumb only, expect warning and .code 16 directive48 .cpu cortex-m349@ STDERR: [[@LINE-1]]:{{[0-9]+}}: warning: new target does not support arm mode, switching to thumb mode50@ CHECK: .cpu cortex-m351@ CHECK: .code 1652 53@ We don't have any ARM-only targets (i.e. v4), so we can't test the forced Thumb->ARM case54