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1@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileCheck %s2@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileCheck %s3@ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileCheck %s4@ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileCheck %s5 6 vadd.f16 d0, d1, d27 vadd.f16 q0, q1, q28@ CHECK: instruction requires: {{full half-float|NEON}}9@ CHECK: instruction requires: {{full half-float|NEON}}10 11 vsub.f16 d0, d1, d212 vsub.f16 q0, q1, q213@ CHECK: instruction requires: {{full half-float|NEON}}14@ CHECK: instruction requires: {{full half-float|NEON}}15 16 vmul.f16 d0, d1, d217 vmul.f16 q0, q1, q218@ CHECK: instruction requires: {{full half-float|NEON}}19@ CHECK: instruction requires: {{full half-float|NEON}}20 21 vmul.f16 d1, d2, d3[2]22 vmul.f16 q4, q5, d6[3]23@ CHECK: instruction requires: {{full half-float|NEON}}24@ CHECK: instruction requires: {{full half-float|NEON}}25 26 vmla.f16 d0, d1, d227 vmla.f16 q0, q1, q228@ CHECK: instruction requires: {{full half-float|NEON}}29@ CHECK: instruction requires: {{full half-float|NEON}}30 31 vmla.f16 d5, d6, d7[2]32 vmla.f16 q5, q6, d7[3]33@ CHECK: instruction requires: {{full half-float|NEON}}34@ CHECK: instruction requires: {{full half-float|NEON}}35 36 vmls.f16 d0, d1, d237 vmls.f16 q0, q1, q238@ CHECK: instruction requires: {{full half-float|NEON}}39@ CHECK: instruction requires: {{full half-float|NEON}}40 41 vmls.f16 d5, d6, d7[2]42 vmls.f16 q5, q6, d7[3]43@ CHECK: instruction requires: {{full half-float|NEON}}44@ CHECK: instruction requires: {{full half-float|NEON}}45 46 vfma.f16 d0, d1, d247 vfma.f16 q0, q1, q248@ CHECK: instruction requires: {{full half-float|NEON}}49@ CHECK: instruction requires: {{full half-float|NEON}}50 51 vfms.f16 d0, d1, d252 vfms.f16 q0, q1, q253@ CHECK: instruction requires: {{full half-float|NEON}}54@ CHECK: instruction requires: {{full half-float|NEON}}55 56 vceq.f16 d2, d3, d457 vceq.f16 q2, q3, q458@ CHECK: instruction requires: {{full half-float|NEON}}59@ CHECK: instruction requires: {{full half-float|NEON}}60 61 vceq.f16 d2, d3, #062 vceq.f16 q2, q3, #063@ CHECK: instruction requires: {{full half-float|NEON}}64@ CHECK: instruction requires: {{full half-float|NEON}}65 66 vcge.f16 d2, d3, d467 vcge.f16 q2, q3, q468@ CHECK: instruction requires: {{full half-float|NEON}}69@ CHECK: instruction requires: {{full half-float|NEON}}70 71 vcge.f16 d2, d3, #072 vcge.f16 q2, q3, #073@ CHECK: instruction requires: {{full half-float|NEON}}74@ CHECK: instruction requires: {{full half-float|NEON}}75 76 vcgt.f16 d2, d3, d477 vcgt.f16 q2, q3, q478@ CHECK: instruction requires: {{full half-float|NEON}}79@ CHECK: instruction requires: {{full half-float|NEON}}80 81 vcgt.f16 d2, d3, #082 vcgt.f16 q2, q3, #083@ CHECK: instruction requires: {{full half-float|NEON}}84@ CHECK: instruction requires: {{full half-float|NEON}}85 86 vcle.f16 d2, d3, d487 vcle.f16 q2, q3, q488@ CHECK: instruction requires: {{full half-float|NEON}}89@ CHECK: instruction requires: {{full half-float|NEON}}90 91 vcle.f16 d2, d3, #092 vcle.f16 q2, q3, #093@ CHECK: instruction requires: {{full half-float|NEON}}94@ CHECK: instruction requires: {{full half-float|NEON}}95 96 vclt.f16 d2, d3, d497 vclt.f16 q2, q3, q498@ CHECK: instruction requires: {{full half-float|NEON}}99@ CHECK: instruction requires: {{full half-float|NEON}}100 101 vclt.f16 d2, d3, #0102 vclt.f16 q2, q3, #0103@ CHECK: instruction requires: {{full half-float|NEON}}104@ CHECK: instruction requires: {{full half-float|NEON}}105 106 vacge.f16 d0, d1, d2107 vacge.f16 q0, q1, q2108@ CHECK: instruction requires: {{full half-float|NEON}}109@ CHECK: instruction requires: {{full half-float|NEON}}110 111 vacgt.f16 d0, d1, d2112 vacgt.f16 q0, q1, q2113@ CHECK: instruction requires: {{full half-float|NEON}}114@ CHECK: instruction requires: {{full half-float|NEON}}115 116 vacle.f16 d0, d1, d2117 vacle.f16 q0, q1, q2118@ CHECK: instruction requires: {{full half-float|NEON}}119@ CHECK: instruction requires: {{full half-float|NEON}}120 121 vaclt.f16 d0, d1, d2122 vaclt.f16 q0, q1, q2123@ CHECK: instruction requires: {{full half-float|NEON}}124@ CHECK: instruction requires: {{full half-float|NEON}}125 126 vabd.f16 d0, d1, d2127 vabd.f16 q0, q1, q2128@ CHECK: instruction requires: {{full half-float|NEON}}129@ CHECK: instruction requires: {{full half-float|NEON}}130 131 vabs.f16 d0, d1132 vabs.f16 q0, q1133@ CHECK: instruction requires: {{full half-float|NEON}}134@ CHECK: instruction requires: {{full half-float|NEON}}135 136 vmax.f16 d0, d1, d2137 vmax.f16 q0, q1, q2138@ CHECK: instruction requires: {{full half-float|NEON}}139@ CHECK: instruction requires: {{full half-float|NEON}}140 141 vmin.f16 d0, d1, d2142 vmin.f16 q0, q1, q2143@ CHECK: instruction requires: {{full half-float|NEON}}144@ CHECK: instruction requires: {{full half-float|NEON}}145 146 vmaxnm.f16 d0, d1, d2147 vmaxnm.f16 q0, q1, q2148@ CHECK: instruction requires: {{full half-float|NEON}}149@ CHECK: instruction requires: {{full half-float|NEON}}150 151 vminnm.f16 d0, d1, d2152 vminnm.f16 q0, q1, q2153@ CHECK: instruction requires: {{full half-float|NEON}}154@ CHECK: instruction requires: {{full half-float|NEON}}155 156 vpadd.f16 d0, d1, d2157@ CHECK: instruction requires: {{full half-float|NEON}}158 159 vpmax.f16 d0, d1, d2160@ CHECK: instruction requires: {{full half-float|NEON}}161 162 vpmin.f16 d0, d1, d2163@ CHECK: instruction requires: {{full half-float|NEON}}164 165 vrecpe.f16 d0, d1166 vrecpe.f16 q0, q1167@ CHECK: instruction requires: {{full half-float|NEON}}168@ CHECK: instruction requires: {{full half-float|NEON}}169 170 vrecps.f16 d0, d1, d2171 vrecps.f16 q0, q1, q2172@ CHECK: instruction requires: {{full half-float|NEON}}173@ CHECK: instruction requires: {{full half-float|NEON}}174 175 vrsqrte.f16 d0, d1176 vrsqrte.f16 q0, q1177@ CHECK: instruction requires: {{full half-float|NEON}}178@ CHECK: instruction requires: {{full half-float|NEON}}179 180 vrsqrts.f16 d0, d1, d2181 vrsqrts.f16 q0, q1, q2182@ CHECK: instruction requires: {{full half-float|NEON}}183@ CHECK: instruction requires: {{full half-float|NEON}}184 185 vneg.f16 d0, d1186 vneg.f16 q0, q1187@ CHECK: instruction requires: {{full half-float|NEON}}188@ CHECK: instruction requires: {{full half-float|NEON}}189 190 vcvt.s16.f16 d0, d1191 vcvt.u16.f16 d0, d1192 vcvt.f16.s16 d0, d1193 vcvt.f16.u16 d0, d1194 vcvt.s16.f16 q0, q1195 vcvt.u16.f16 q0, q1196 vcvt.f16.s16 q0, q1197 vcvt.f16.u16 q0, q1198@ CHECK: instruction requires: {{full half-float|NEON}}199@ CHECK: instruction requires: {{full half-float|NEON}}200@ CHECK: instruction requires: {{full half-float|NEON}}201@ CHECK: instruction requires: {{full half-float|NEON}}202@ CHECK: instruction requires: {{full half-float|NEON}}203@ CHECK: instruction requires: {{full half-float|NEON}}204@ CHECK: instruction requires: {{full half-float|NEON}}205@ CHECK: instruction requires: {{full half-float|NEON}}206 207 vcvta.s16.f16 d0, d1208 vcvta.s16.f16 q0, q1209 vcvta.u16.f16 d0, d1210 vcvta.u16.f16 q0, q1211@ CHECK: instruction requires: {{full half-float|NEON}}212@ CHECK: instruction requires: {{full half-float|NEON}}213@ CHECK: instruction requires: {{full half-float|NEON}}214@ CHECK: instruction requires: {{full half-float|NEON}}215 216 vcvtm.s16.f16 d0, d1217 vcvtm.s16.f16 q0, q1218 vcvtm.u16.f16 d0, d1219 vcvtm.u16.f16 q0, q1220@ CHECK: instruction requires: {{full half-float|NEON}}221@ CHECK: instruction requires: {{full half-float|NEON}}222@ CHECK: instruction requires: {{full half-float|NEON}}223@ CHECK: instruction requires: {{full half-float|NEON}}224 225 vcvtn.s16.f16 d0, d1226 vcvtn.s16.f16 q0, q1227 vcvtn.u16.f16 d0, d1228 vcvtn.u16.f16 q0, q1229@ CHECK: instruction requires: {{full half-float|NEON}}230@ CHECK: instruction requires: {{full half-float|NEON}}231@ CHECK: instruction requires: {{full half-float|NEON}}232@ CHECK: instruction requires: {{full half-float|NEON}}233 234 vcvtp.s16.f16 d0, d1235 vcvtp.s16.f16 q0, q1236 vcvtp.u16.f16 d0, d1237 vcvtp.u16.f16 q0, q1238@ CHECK: instruction requires: {{full half-float|NEON}}239@ CHECK: instruction requires: {{full half-float|NEON}}240@ CHECK: instruction requires: {{full half-float|NEON}}241@ CHECK: instruction requires: {{full half-float|NEON}}242 243 244 vcvt.s16.f16 d0, d1, #1245 vcvt.u16.f16 d0, d1, #2246 vcvt.f16.s16 d0, d1, #3247 vcvt.f16.u16 d0, d1, #4248 vcvt.s16.f16 q0, q1, #5249 vcvt.u16.f16 q0, q1, #6250 vcvt.f16.s16 q0, q1, #7251 vcvt.f16.u16 q0, q1, #8252@ CHECK: instruction requires: {{full half-float|NEON}}253@ CHECK: instruction requires: {{full half-float|NEON}}254@ CHECK: instruction requires: {{full half-float|NEON}}255@ CHECK: instruction requires: {{full half-float|NEON}}256@ CHECK: instruction requires: {{full half-float|NEON}}257@ CHECK: instruction requires: {{full half-float|NEON}}258@ CHECK: instruction requires: {{full half-float|NEON}}259@ CHECK: instruction requires: {{full half-float|NEON}}260 261 vrinta.f16.f16 d0, d1262 vrinta.f16.f16 q0, q1263@ CHECK: instruction requires: {{full half-float|NEON}}264@ CHECK: instruction requires: {{full half-float|NEON}}265 266 vrintm.f16.f16 d0, d1267 vrintm.f16.f16 q0, q1268@ CHECK: instruction requires: {{full half-float|NEON}}269@ CHECK: instruction requires: {{full half-float|NEON}}270 271 vrintn.f16.f16 d0, d1272 vrintn.f16.f16 q0, q1273@ CHECK: instruction requires: {{full half-float|NEON}}274@ CHECK: instruction requires: {{full half-float|NEON}}275 276 vrintp.f16.f16 d0, d1277 vrintp.f16.f16 q0, q1278@ CHECK: instruction requires: {{full half-float|NEON}}279@ CHECK: instruction requires: {{full half-float|NEON}}280 281 vrintx.f16.f16 d0, d1282 vrintx.f16.f16 q0, q1283@ CHECK: instruction requires: {{full half-float|NEON}}284@ CHECK: instruction requires: {{full half-float|NEON}}285 286 vrintz.f16.f16 d0, d1287 vrintz.f16.f16 q0, q1288@ CHECK: instruction requires: {{full half-float|NEON}}289@ CHECK: instruction requires: {{full half-float|NEON}}290