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1@ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8d16sp -show-encoding < %s 2>&1 | FileCheck %s2 3vmaxnm.f32 s4, d5, q14@ CHECK: error: invalid instruction5vmaxnm.f64.f64 s4, d5, q16@ CHECK: error: invalid instruction7vmaxnmge.f64.f64 s4, d5, q18@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified9 10vcvta.s32.f32 s1, s211@ CHECK: error: instruction requires: FPARMv812vcvtp.u32.f32 s1, d213@ CHECK: error: operand must be a register in range [d0, d31]14vcvtp.f32.u32 d1, q215@ CHECK: error: invalid instruction16vcvtplo.f32.u32 s1, s217@ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified18 19vrinta.f64.f64 s3, d1220@ CHECK: error: invalid instruction21vrintn.f32 d3, q1222@ CHECK: error: invalid instruction, any one of the following would fix this:23@ CHECK: note: operand must be a register in range [d0, d31]24@ CHECK: note: operand must be a register in range [q0, q15]25vrintz.f32 d3, q1226@ CHECK: error: invalid instruction, any one of the following would fix this:27@ CHECK: note: operand must be a register in range [d0, d31]28@ CHECK: note: operand must be a register in range [q0, q15]29vrintmge.f32.f32 d3, d430@ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified31 32aesd.8 q0, s133@ CHECK: error: operand must be a register in range [q0, q15]34aese.8 s0, q135@ CHECK: error: operand must be a register in range [q0, q15]36aesimc.8 s0, q137@ CHECK: error: operand must be a register in range [q0, q15]38aesmc.8 q0, d139@ CHECK: error: operand must be a register in range [q0, q15]40aesdge.8 q0, q141@ CHECK: error: instruction 'aesd' is not predicable, but condition code specified42 43sha1h.32 d0, q144@ CHECK: error: operand must be a register in range [q0, q15]45sha1su1.32 q0, s146@ CHECK: error: operand must be a register in range [q0, q15]47sha256su0.32 s0, q148@ CHECK: error: operand must be a register in range [q0, q15]49sha1heq.32 q0, q150@ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified51 52sha1c.32 s0, d1, q253@ CHECK: error: invalid instruction54sha1m.32 q0, s1, q255@ CHECK: error: operand must be a register in range [q0, q15]56sha1p.32 s0, q1, q257@ CHECK: error: operand must be a register in range [q0, q15]58sha1su0.32 d0, q1, q259@ CHECK: error: operand must be a register in range [q0, q15]60sha256h.32 q0, s1, q261@ CHECK: error: operand must be a register in range [q0, q15]62sha256h2.32 q0, q1, s263@ CHECK: error: operand must be a register in range [q0, q15]64sha256su1.32 s0, d1, q265@ CHECK: error: invalid instruction66sha256su1lt.32 q0, d1, q267@ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified68 69vmull.p64 q0, s1, s370@ CHECK: error: invalid instruction71vmull.p64 s1, d2, d372@ CHECK: error: operand must be a register in range [q0, q15]73vmullge.p64 q0, d16, d1774@ CHECK: error: instruction 'vmull' is not predicable, but condition code specified75 76// These instructions are predicable in VFP but not in NEON77vrintzeq.f32 d0, d178vrintxgt.f32 d0, d179@ CHECK: error: invalid operand for instruction80@ CHECK: error: invalid operand for instruction81