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1// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefixes=CHECK-NONARM,CHECK-THUMBV7 %s2// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefixes=CHECK-NONARM,CHECK-THUMBV8 %s3// RUN: llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK-ARM %s4 5 // lsl #0 is actually mov, so here we check that it behaves the same as6 // mov with regards to the permitted registers7 8 // Using PC is invalid in thumb9 lsl pc, r0, #010 lsl r0, pc, #011 lsl pc, pc, #012 lsls pc, r0, #013 lsls r0, pc, #014 lsls pc, pc, #015 16// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:17// CHECK-NONARM-NEXT: lsl pc, r0, #018// CHECK-NONARM: note: instruction requires: arm-mode19// CHECK-NONARM: note: operand must be a register in range [r0, r14]20 21// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:22// CHECK-NONARM-NEXT: lsl r0, pc, #023// CHECK-NONARM: note: instruction requires: arm-mode24// CHECK-NONARM: note: operand must be a register in range [r0, r14]25 26// CHECK-NONARM: error: instruction requires: arm-mode27// CHECK-NONARM-NEXT: lsl pc, pc, #028 29// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:30// CHECK-NONARM-NEXT: lsls pc, r0, #031// CHECK-NONARM: note: instruction requires: arm-mode32// CHECK-NONARM: note: operand must be a register in range [r0, r14]33 34// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:35// CHECK-NONARM-NEXT: lsls r0, pc, #036// CHECK-NONARM: note: instruction requires: arm-mode37// CHECK-NONARM: note: operand must be a register in range [r0, r14]38 39// CHECK-NONARM: error: instruction requires: arm-mode40// CHECK-NONARM-NEXT: lsls pc, pc, #041 42// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]43// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]44// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]45// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]46// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]47// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]48 49 mov pc, r0, lsl #050 mov r0, pc, lsl #051 mov pc, pc, lsl #052 movs pc, r0, lsl #053 movs r0, pc, lsl #054 movs pc, pc, lsl #055 56// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:57// CHECK-NONARM-NEXT: mov pc, r0, lsl #058// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r1459// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]60// CHECK-NONARM: note: operand must be a register in range [r0, r15]61 62// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:63// CHECK-NONARM-NEXT: mov r0, pc, lsl #064// CHECK-NONARM: note: invalid operand for instruction65// CHECK-NONARM: note: invalid operand for instruction66// CHECK-NONARM: note: operand must be an immediate in the range [256,65535]67// CHECK-NONARM: note: operand must be a register in range [r0, r15]68 69// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:70// CHECK-NONARM-NEXT: mov pc, pc, lsl #071// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r1472// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]73// CHECK-NONARM: note: operand must be a register in range [r0, r15]74 75// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:76// CHECK-NONARM-NEXT: movs pc, r0, lsl #077// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r1478// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]79// CHECK-NONARM: note: invalid operand for instruction80 81// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:82// CHECK-NONARM-NEXT: movs r0, pc, lsl #083// CHECK-NONARM: note: operand must be a register in range [r0, r14]84// CHECK-NONARM: note: invalid operand for instruction85// CHECK-NONARM: note: invalid operand for instruction86 87// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:88// CHECK-NONARM-NEXT: movs pc, pc, lsl #089// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r1490// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]91// CHECK-NONARM: note: invalid operand for instruction92 93// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]94// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]95// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]96// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]97// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]98// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]99 100 // Using SP is invalid before ARMv8 in thumb unless non-flags-setting101 // and one of the source and destination is not SP102 lsl sp, sp, #0103 lsls sp, sp, #0104 lsls r0, sp, #0105 lsls sp, r0, #0106 107// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:108// CHECK-THUMBV7-NEXT: lsl sp, sp, #0109// CHECK-THUMBV7: instruction requires: arm-mode110// CHECK-THUMBV7: instruction variant requires ARMv8 or later111// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:112// CHECK-THUMBV7-NEXT: lsls sp, sp, #0113// CHECK-THUMBV7: instruction requires: arm-mode114// CHECK-THUMBV7: instruction variant requires ARMv8 or later115// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:116// CHECK-THUMBV7-NEXT: lsls r0, sp, #0117// CHECK-THUMBV7: instruction requires: arm-mode118// CHECK-THUMBV7: instruction variant requires ARMv8 or later119// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:120// CHECK-THUMBV7-NEXT: lsls sp, r0, #0121// CHECK-THUMBV7: instruction requires: arm-mode122// CHECK-THUMBV7: instruction variant requires ARMv8 or later123 124// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]125// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]126// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]127// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]128 129 mov sp, sp, lsl #0130 movs sp, sp, lsl #0131 movs r0, sp, lsl #0132 movs sp, r0, lsl #0133 134// FIXME: We should consistently have the "requires ARMv8" error here135// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:136// CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0137// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14138// CHECK-THUMBV7: note: operand must be a register in range [r0, r15]139 140// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:141// CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0142// CHECK-THUMBV7: note: operand must be a register in range [r0, r14]143// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14144 145// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:146// CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0147// CHECK-THUMBV7: note: operand must be a register in range [r0, r14]148// CHECK-THUMBV7: note: invalid operand for instruction149// CHECK-THUMBV7: note: instruction variant requires ARMv8 or later150 151// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:152// CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0153// CHECK-THUMBV7: note: operand must be a register in range [r0, r14]154// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14155 156// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]157// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]158// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]159// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]160