238 lines · plain
1# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \2# RUN: | FileCheck --check-prefix=CHECK %s3# RUN: FileCheck --check-prefix=ERROR < %t %s4# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \5# RUN: | FileCheck --check-prefix=CHECK %s6# RUN: FileCheck --check-prefix=ERROR < %t %s7 8# CHECK: vabav.s8 r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]9vabav.s8 r0, q1, q310 11# CHECK: vabav.s16 r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]12vabav.s16 r0, q1, q313 14# CHECK: vabav.s32 r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]15vabav.s32 r0, q1, q316 17# CHECK: vabav.u8 r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]18vabav.u8 r0, q1, q319 20# CHECK: vabav.u16 r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]21vabav.u16 r0, q1, q322 23# CHECK: vabav.u32 r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]24vabav.u32 r0, q1, q325 26# CHECK: vaddv.s16 lr, q0 @ encoding: [0xf5,0xee,0x00,0xef]27vaddv.s16 lr, q028 29# ERROR: [[@LINE+1]]:11: {{error|note}}: operand must be an even-numbered register30vaddv.s16 r1, q031 32# CHECK: vpte.i8 eq, q0, q033# CHECK: vaddvt.s16 r0, q6 @ encoding: [0xf5,0xee,0x0c,0x0f]34# CHECK: vaddve.s16 r0, q6 @ encoding: [0xf5,0xee,0x0c,0x0f]35vpte.i8 eq, q0, q036vaddvt.s16 r0, q637vaddve.s16 r0, q638 39# CHECK: vaddva.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]40vaddva.s16 lr, q041 42# CHECK: vpte.i8 eq, q0, q043# CHECK: vaddvat.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]44# CHECK: vaddvae.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]45vpte.i8 eq, q0, q046vaddvat.s16 lr, q047vaddvae.s16 lr, q048 49# CHECK: vaddlv.s32 r0, r9, q2 @ encoding: [0xc9,0xee,0x04,0x0f]50vaddlv.s32 r0, r9, q251 52# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]53vaddlv.s32 r0, r2, q254 55# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register56vaddlv.s32 r1, r3, q257 58# CHECK: vaddlv.u32 r0, r1, q1 @ encoding: [0x89,0xfe,0x02,0x0f]59vaddlv.u32 r0, r1, q160 61# CHECK: vminv.s8 lr, q0 @ encoding: [0xe2,0xee,0x80,0xef]62vminv.s8 lr, q063 64# CHECK: vminv.s16 lr, q0 @ encoding: [0xe6,0xee,0x80,0xef]65vminv.s16 lr, q066 67# CHECK: vminv.s32 lr, q2 @ encoding: [0xea,0xee,0x84,0xef]68vminv.s32 lr, q269 70# CHECK: vminv.u8 r0, q0 @ encoding: [0xe2,0xfe,0x80,0x0f]71vminv.u8 r0, q072 73# CHECK: vminv.u32 r10, q3 @ encoding: [0xea,0xfe,0x86,0xaf]74vminv.u32 r10, q375 76# CHECK: vminav.s16 r0, q0 @ encoding: [0xe4,0xee,0x80,0x0f]77vminav.s16 r0, q078 79# CHECK: vminav.s8 r0, q1 @ encoding: [0xe0,0xee,0x82,0x0f]80vminav.s8 r0, q181 82# CHECK: vminav.s32 lr, q1 @ encoding: [0xe8,0xee,0x82,0xef]83vminav.s32 lr, q184 85# CHECK: vmaxv.s8 lr, q4 @ encoding: [0xe2,0xee,0x08,0xef]86vmaxv.s8 lr, q487 88# CHECK: vmaxv.s16 lr, q0 @ encoding: [0xe6,0xee,0x00,0xef]89vmaxv.s16 lr, q090 91# CHECK: vmaxv.s32 r1, q1 @ encoding: [0xea,0xee,0x02,0x1f]92vmaxv.s32 r1, q193 94# CHECK: vmaxv.u8 r0, q4 @ encoding: [0xe2,0xfe,0x08,0x0f]95vmaxv.u8 r0, q496 97# CHECK: vmaxv.u16 r0, q1 @ encoding: [0xe6,0xfe,0x02,0x0f]98vmaxv.u16 r0, q199 100# CHECK: vmaxv.u32 r1, q0 @ encoding: [0xea,0xfe,0x00,0x1f]101vmaxv.u32 r1, q0102 103# CHECK: vmaxav.s8 lr, q6 @ encoding: [0xe0,0xee,0x0c,0xef]104vmaxav.s8 lr, q6105 106# CHECK: vmaxav.s16 r0, q6 @ encoding: [0xe4,0xee,0x0c,0x0f]107vmaxav.s16 r0, q6108 109# CHECK: vmaxav.s32 r10, q7 @ encoding: [0xe8,0xee,0x0e,0xaf]110vmaxav.s32 r10, q7111 112# CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]113vmladav.s16 lr, q0, q7114 115# CHECK: vmlav.s32 lr, q0, q4 @ encoding: [0xf1,0xee,0x08,0xee]116vmladav.s32 lr, q0, q4117 118# CHECK: vmlav.u16 lr, q0, q7 @ encoding: [0xf0,0xfe,0x0e,0xee]119vmladav.u16 lr, q0, q7120 121# CHECK: vmlav.u32 lr, q0, q0 @ encoding: [0xf1,0xfe,0x00,0xee]122vmladav.u32 lr, q0, q0123 124# CHECK: vmlava.s16 lr, q0, q4 @ encoding: [0xf0,0xee,0x28,0xee]125vmladava.s16 lr, q0, q4126 127# CHECK: vmladavx.s16 r0, q0, q7 @ encoding: [0xf0,0xee,0x0e,0x1e]128vmladavx.s16 r0, q0, q7129 130# CHECK: vmladavax.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x2e,0xfe]131vmladavax.s16 lr, q0, q7132 133# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction134vmladavax.u16 r0, q4, q5135 136# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction137vmladavx.u16 r0, q4, q5138 139# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction140vmladavax.u32 r0, q4, q5141 142# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction143vmladavx.u32 r0, q4, q5144 145# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction146vmladavax.u8 r0, q4, q5147 148# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction149vmladavx.u8 r0, q4, q5150 151# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction152vmlaldavax.u16 r2, r3, q4, q5153 154# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction155vmlaldavx.u16 r2, r3, q4, q5156 157# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction158vmlaldavax.u32 r2, r3, q4, q5159 160# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction161vmlaldavx.u32 r2, r3, q4, q5162 163# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction164vrmlaldavhax.u32 r2, r3, q4, q5165 166# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction167vrmlaldavhx.u32 r2, r3, q4, q5168 169# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]170vmladav.s8 lr, q3, q0171 172# CHECK: vmlav.u8 lr, q1, q7 @ encoding: [0xf2,0xfe,0x0e,0xef]173vmladav.u8 lr, q1, q7174 175# CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]176vrmlaldavh.s32 lr, r1, q6, q2177 178# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]179vrmlaldavh.u32 lr, r1, q5, q2180 181# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]182vrmlaldavh.u32 lr, r1, q5, q2183 184# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register185vrmlaldavh.u32 r1, r3, q5, q2186 187# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]188vrmlaldavh.u32 r2, r4, q5, q2189 190# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0 @ encoding: [0x86,0xee,0x20,0xff]191vrmlaldavhax.s32 lr, r1, q3, q0192 193# CHECK: vrmlsldavh.s32 lr, r11, q6, q5 @ encoding: [0xdc,0xfe,0x0b,0xee]194vrmlsldavh.s32 lr, r11, q6, q5195 196# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]197vmlsdav.s16 lr, q0, q3198 199# CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]200vrmlalvh.s32 lr, r1, q6, q2201 202# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]203vrmlalvh.u32 lr, r1, q5, q2204 205# CHECK: vrmlalvha.s32 lr, r1, q3, q6 @ encoding: [0x86,0xee,0x2c,0xef]206vrmlalvha.s32 lr, r1, q3, q6207 208# CHECK: vrmlalvha.u32 lr, r1, q7, q1 @ encoding: [0x8e,0xfe,0x22,0xef]209vrmlalvha.u32 lr, r1, q7, q1210 211# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]212vmlsdav.s16 lr, q0, q3213 214# CHECK: vmlsdav.s32 lr, q2, q6 @ encoding: [0xf5,0xee,0x0d,0xee]215vmlsdav.s32 lr, q2, q6216 217# CHECK: vpte.i8 eq, q0, q0218# CHECK: vmlsdavaxt.s16 lr, q1, q4 @ encoding: [0xf2,0xee,0x29,0xfe]219# CHECK: vmlsdavaxe.s16 lr, q1, q4 @ encoding: [0xf2,0xee,0x29,0xfe]220vpte.i8 eq, q0, q0221vmlsdavaxt.s16 lr, q1, q4222vmlsdavaxe.s16 lr, q1, q4223 224# CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]225vmlav.s16 lr, q0, q7226 227# CHECK: vmlalv.s16 lr, r1, q4, q1 @ encoding: [0x88,0xee,0x02,0xee]228vmlaldav.s16 lr, r1, q4, q1229 230# CHECK: vmlalv.s32 lr, r11, q4, q1 @ encoding: [0xd9,0xee,0x02,0xee]231vmlaldav.s32 lr, r11, q4, q1232 233# CHECK: vmlalv.s32 r0, r1, q7, q6 @ encoding: [0x8f,0xee,0x0c,0x0e]234vmlalv.s32 r0, r1, q7, q6235 236# CHECK: vmlalv.u16 lr, r11, q5, q4 @ encoding: [0xda,0xfe,0x08,0xee]237vmlalv.u16 lr, r11, q5, q4238