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1// RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s2 3 .text4 .thumb5 6 // Check that the correct encoding of the add and sub instructions is7 // selected, for all combinations of flag-setting, condition and 2- or8 // 3-operand syntax.9 10 .arch armv6-m11 add r0, r0, r1 // T212 add r0, r1 // T213 adds r0, r0, r1 // T114 adds r0, r1 // T115// CHECK: add r0, r1 @ encoding: [0x08,0x44]16// CHECK: add r0, r1 @ encoding: [0x08,0x44]17// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]18// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]19 20 .arch armv7-m21 add r0, r0, r1 // T2, T322 add r0, r1 // T2, T323 adds r0, r0, r1 // T1, T324 adds r0, r1 // T1, T325// CHECK: add r0, r1 @ encoding: [0x08,0x44]26// CHECK: add r0, r1 @ encoding: [0x08,0x44]27// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]28// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]29 30 itttt eq31// CHECK: itttt eq @ encoding: [0x01,0xbf]32 addeq r0, r0, r1 // T1, T2, T333 addeq r0, r1 // T2, T1, T334 addseq r0, r0, r1 // T335 addseq r0, r1 // T336 // NOTE: Both T1 and T2 are valid for these two instructions, which one is37 // the preferred varies depending on whether the 2- or 3-operand syntax was38 // used.39// CHECK: addeq r0, r0, r1 @ encoding: [0x40,0x18]40// CHECK: addeq r0, r1 @ encoding: [0x08,0x44]41// CHECK: addseq.w r0, r0, r1 @ encoding: [0x10,0xeb,0x01,0x00]42// CHECK: addseq.w r0, r0, r1 @ encoding: [0x10,0xeb,0x01,0x00]43 44 .arch armv6-m45 // NOTE: There is no non-flag-setting sub instruction for v6-M46 subs r0, r0, r1 // T1, T247 subs r0, r1 // T1, T248// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]49// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]50 51 .arch armv7-m52 sub r0, r0, r1 // T253 sub r0, r1 // T254 subs r0, r0, r1 // T1, T255 subs r0, r1 // T1, T256// CHECK: sub.w r0, r0, r1 @ encoding: [0xa0,0xeb,0x01,0x00]57// CHECK: sub.w r0, r0, r1 @ encoding: [0xa0,0xeb,0x01,0x00]58// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]59// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]60 61 itttt eq62// CHECK: itttt eq @ encoding: [0x01,0xbf]63 subeq r0, r0, r1 // T1, T264 subeq r0, r1 // T1, T265 subseq r0, r0, r1 // T266 subseq r0, r1 // T267// CHECK: subeq r0, r0, r1 @ encoding: [0x40,0x1a]68// CHECK: subeq r0, r0, r1 @ encoding: [0x40,0x1a]69// CHECK: subseq.w r0, r0, r1 @ encoding: [0xb0,0xeb,0x01,0x00]70// CHECK: subseq.w r0, r0, r1 @ encoding: [0xb0,0xeb,0x01,0x00]71