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1@ RUN: not llvm-mc -triple=thumbv6-apple-darwin -o /dev/null < %s 2>&1 \2@ RUN: | FileCheck --check-prefix=CHECK-ERRORS %s3@ RUN: not llvm-mc -triple=thumbv5-apple-darwin -o /dev/null < %s 2>&1 \4@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V5 %s5@ RUN: not llvm-mc -triple=thumbv7m -o /dev/null < %s 2>&1 \6@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V7M %s7@ RUN: not llvm-mc -triple=thumbv8 -o /dev/null < %s 2>&1 \8@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V8 %s9 10@ Check for various assembly diagnostic messages on invalid input.11 12@ ADD instruction w/o 'S' suffix.13 add r1, r2, r314@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:15@ CHECK-ERRORS: add r1, r2, r316@ CHECK-ERRORS: ^17@ CHECK-ERRORS: note: instruction requires: arm-mode18@ CHECK-ERRORS: note: instruction requires: thumb219@ CHECK-ERRORS: note: invalid operand for instruction20@ CHECK-ERRORS: note: operand must be an immediate in the range [0,7]21@ CHECK-ERRORS: note: no flag-preserving variant of this instruction available22 23@ Instructions which require v6+ for both registers to be low regs.24 add r2, r325 mov r2, r326@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:27@ CHECK-ERRORS: add r2, r328@ CHECK-ERRORS: ^29@ CHECK-ERRORS: note: instruction variant requires Thumb230@ CHECK-ERRORS: note: operand must be a register sp31@ CHECK-ERRORS-V5: error: invalid instruction, any one of the following would fix this:32@ CHECK-ERRORS-V5: mov r2, r333@ CHECK-ERRORS-V5: ^34@ CHECK-ERRORS-V5: note: instruction requires: arm-mode35@ CHECK-ERRORS-V5: note: operand must be an immediate in the range [0,255] or a relocatable expression36@ CHECK-ERRORS-V5: note: instruction variant requires ARMv6 or later37 38@ Immediates where registers were expected39 adds #0, r1, r240 adds r0, #1, r241@ CHECK-ERRORS: error: operand must be a register in range [r0, r7]42@ CHECK-ERRORS: adds #0, r1, r243@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:44@ CHECK-ERRORS: adds r0, #1, r245@ CHECK-ERRORS: note: operand must be a register in range [r0, r7]46@ CHECK-ERRORS: note: too many operands for instruction47 48@ Out of range immediates for ASR instruction.49 asrs r2, r3, #3350@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:51@ CHECK-ERRORS: asrs r2, r3, #3352@ CHECK-ERRORS: ^53@ CHECK-ERRORS: note: operand must be an immediate in the range [1,32]54@ CHECK-ERRORS: note: too many operands for instruction55 56@ Out of range immediates for BKPT instruction.57 bkpt #25658 bkpt #-159@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:60@ CHECK-ERRORS: bkpt #25661@ CHECK-ERRORS: ^62@ CHECK-ERRORS: note: instruction requires: arm-mode63@ CHECK-ERRORS: note: operand must be an immediate in the range [0,255]64@ CHECK-ERRORS: note: too many operands for instruction65 66@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:67@ CHECK-ERRORS: bkpt #-168@ CHECK-ERRORS: ^69@ CHECK-ERRORS: note: operand must be an immediate in the range [0,255]70@ CHECK-ERRORS: note: too many operands for instruction71 72@ Out of range immediates for v8 HLT instruction.73 hlt #6474 hlt #-175@CHECK-ERRORS: error: invalid instruction76@CHECK-ERRORS: hlt #6477@CHECK-ERRORS: ^78@CHECK-ERRORS-V8: error: invalid instruction, any one of the following would fix this:79@CHECK-ERRORS-V8: hlt #6480@CHECK-ERRORS-V8: ^81@CHECK-ERRORS-V8: note: instruction requires: arm-mode82@CHECK-ERRORS-V8: operand must be an immediate in the range [0,63]83@CHECK-ERRORS: error: invalid instruction84@CHECK-ERRORS: hlt #-185@CHECK-ERRORS: ^86@CHECK-ERRORS-V8: error: operand must be an immediate in the range [0,63]87@CHECK-ERRORS-V8: hlt #-188@CHECK-ERRORS-V8: ^89 90@ Invalid writeback and register lists for LDM91 ldm r2!, {r5, r8}92 ldm r2, {r5, r7}93 ldm r2!, {r2, r3, r4}94 ldm r2!, {r2, r3, r4, r10}95 ldmdb r2!, {r2, r3, r4}96 ldm r0, {r2, sp}97 ldmia r0, {r2-r3, sp}98 ldmia r0!, {r2-r3, sp}99 ldmfd r2, {r1, r3-r6, sp}100 ldmfd r2!, {r1, r3-r6, sp}101 ldmdb r1, {r2, r3, sp}102 ldmdb r1!, {r2, r3, sp} 103@ CHECK-ERRORS: error: registers must be in range r0-r7104@ CHECK-ERRORS: ldm r2!, {r5, r8}105@ CHECK-ERRORS: ^106@ CHECK-ERRORS: error: writeback operator '!' expected107@ CHECK-ERRORS: ldm r2, {r5, r7}108@ CHECK-ERRORS: ^109@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list110@ CHECK-ERRORS: ldm r2!, {r2, r3, r4}111@ CHECK-ERRORS: ^112@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list113@ CHECK-ERRORS-V8: ldm r2!, {r2, r3, r4, r10}114@ CHECK-ERRORS-V8: ^115@ CHECK-ERRORS-V8: error: writeback register not allowed in register list116@ CHECK-ERRORS-V8: ldmdb r2!, {r2, r3, r4}117@ CHECK-ERRORS-V8: ^118@ CHECK-ERRORS-V7M: error: SP may not be in the register list119@ CHECK-ERRORS-V7M: ldm r0, {r2, sp}120@ CHECK-ERRORS-V7M: ^121@ CHECK-ERRORS-V7M: error: SP may not be in the register list122@ CHECK-ERRORS-V7M: ldmia r0, {r2-r3, sp}123@ CHECK-ERRORS-V7M: ^124@ CHECK-ERRORS-V7M: error: SP may not be in the register list125@ CHECK-ERRORS-V7M: ldmia r0!, {r2-r3, sp}126@ CHECK-ERRORS-V7M: ^127@ CHECK-ERRORS-V7M: error: SP may not be in the register list128@ CHECK-ERRORS-V7M: ldmfd r2, {r1, r3-r6, sp}129@ CHECK-ERRORS-V7M: ^130@ CHECK-ERRORS-V7M: error: SP may not be in the register list131@ CHECK-ERRORS-V7M: ldmfd r2!, {r1, r3-r6, sp}132@ CHECK-ERRORS-V7M: ^133@ CHECK-ERRORS-V7M: error: SP may not be in the register list134@ CHECK-ERRORS-V7M: ldmdb r1, {r2, r3, sp}135@ CHECK-ERRORS-V7M: ^136@ CHECK-ERRORS-V7M: error: SP may not be in the register list137@ CHECK-ERRORS-V7M: ldmdb r1!, {r2, r3, sp}138@ CHECK-ERRORS-V7M: ^139 140@ Invalid writeback and register lists for PUSH/POP141 pop {r1, r2, r10}142 push {r8, r9}143@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc144@ CHECK-ERRORS: pop {r1, r2, r10}145@ CHECK-ERRORS: ^146@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr147@ CHECK-ERRORS: push {r8, r9}148@ CHECK-ERRORS: ^149 150 151@ Invalid writeback and register lists for STM152 stm r1, {r2, r6}153 stm r1!, {r2, r9}154 stm r2!, {r2, r9}155 stmdb r2!, {r0, r2}156 stm r1!, {r2, sp}157 stmia r4!, {r0-r3, sp}158 stmdb r1, {r2, r3, sp}159 stmdb r1!, {r2, r3, sp}160@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:161@ CHECK-ERRORS: stm r1, {r2, r6}162@ CHECK-ERRORS: ^163@ CHECK-ERRORS: note: instruction requires: thumb2164@ CHECK-ERRORS: note: instruction requires: arm-mode165@ CHECK-ERRORS: error: registers must be in range r0-r7166@ CHECK-ERRORS: stm r1!, {r2, r9}167@ CHECK-ERRORS: ^168@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list169@ CHECK-ERRORS-V8: stm r2!, {r2, r9}170@ CHECK-ERRORS-V8: ^171@ CHECK-ERRORS-V8: error: writeback register not allowed in register list172@ CHECK-ERRORS-V8: stmdb r2!, {r0, r2}173@ CHECK-ERRORS-V8: ^174@ CHECK-ERRORS-V7M: error: SP may not be in the register list175@ CHECK-ERRORS-V7M: stm r1!, {r2, sp}176@ CHECK-ERRORS-V7M: ^177@ CHECK-ERRORS-V7M: error: SP may not be in the register list178@ CHECK-ERRORS-V7M: stmia r4!, {r0-r3, sp}179@ CHECK-ERRORS-V7M: ^180@ CHECK-ERRORS-V7M: error: SP may not be in the register list181@ CHECK-ERRORS-V7M: stmdb r1, {r2, r3, sp}182@ CHECK-ERRORS-V7M: ^183@ CHECK-ERRORS-V7M: error: SP may not be in the register list184@ CHECK-ERRORS-V7M: stmdb r1!, {r2, r3, sp}185@ CHECK-ERRORS-V7M: ^186 187@ Out of range immediates for LSL instruction.188 lsls r4, r5, #-1189 lsls r4, r5, #32190@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:191@ CHECK-ERRORS: lsls r4, r5, #-1192@ CHECK-ERRORS: ^193@ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]194@ CHECK-ERRORS: note: too many operands for instruction195@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:196@ CHECK-ERRORS: lsls r4, r5, #32197@ CHECK-ERRORS: ^198@ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]199@ CHECK-ERRORS: note: too many operands for instruction200 201@ Out of range immediates for MOVS/ADDS instruction.202 movs r3, #-1203 adds r3, #256204@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:205@ CHECK-ERRORS-NEXT: movs r3, #-1206@ CHECK-ERRORS-NEXT: ^207@ CHECK-ERRORS: note: operand must be an immediate in the range [0,255] or a relocatable expression208@ CHECK-ERRORS-NEXT: movs r3, #-1209@ CHECK-ERRORS-NEXT: ^210@ CHECK-ERRORS: note: operand must be a register in range [r0, r7]211@ CHECK-ERRORS-NEXT: movs r3, #-1212@ CHECK-ERRORS-NEXT: ^213@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:214@ CHECK-ERRORS-NEXT: adds r3, #256215@ CHECK-ERRORS-NEXT: ^216@ CHECK-ERRORS: note: instruction requires: thumb2217@ CHECK-ERRORS-NEXT: adds r3, #256218@ CHECK-ERRORS-NEXT: ^219@ CHECK-ERRORS: note: invalid operand for instruction220@ CHECK-ERRORS-NEXT: adds r3, #256221@ CHECK-ERRORS-NEXT: ^222@ CHECK-ERRORS-NEXT: note: operand must be an immediate in the range [0,255] or a relocatable expression223@ CHECK-ERRORS-NEXT: adds r3, #256224@ CHECK-ERRORS-NEXT: ^225@ CHECK-ERRORS-NEXT: note: operand must be a register in range [r0, r7]226@ CHECK-ERRORS-NEXT: adds r3, #256227@ CHECK-ERRORS-NEXT: ^228 229@ Mismatched source/destination operands for MUL instruction.230 muls r1, r2, r3231@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:232@ CHECK-ERRORS: muls r1, r2, r3233@ CHECK-ERRORS: ^234@ CHECK-ERRORS: note: destination register must match a source register235@ CHECK-ERRORS: note: too many operands for instruction236 237@ Out of range immediates for STR instruction.238 str r2, [r7, #-1]239 str r5, [r1, #3]240 str r3, [r7, #128]241@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:242@ CHECK-ERRORS: str r2, [r7, #-1]243@ CHECK-ERRORS: ^244@ CHECK-ERRORS: note: instruction requires: thumb2245@ CHECK-ERRORS: note: instruction requires: arm-mode246@ CHECK-ERRORS: note: invalid operand for instruction247@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:248@ CHECK-ERRORS: str r5, [r1, #3]249@ CHECK-ERRORS: ^250@ CHECK-ERRORS: note: instruction requires: thumb2251@ CHECK-ERRORS: note: instruction requires: arm-mode252@ CHECK-ERRORS: note: invalid operand for instruction253@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:254@ CHECK-ERRORS: str r3, [r7, #128]255@ CHECK-ERRORS: ^256@ CHECK-ERRORS: note: instruction requires: thumb2257@ CHECK-ERRORS: note: instruction requires: arm-mode258@ CHECK-ERRORS: note: invalid operand for instruction259 260@ Out of range immediate for SVC instruction.261 svc #-1262 svc #256263@ CHECK-ERRORS: error: operand must be an immediate in the range [0,255]264@ CHECK-ERRORS: svc #-1265@ CHECK-ERRORS: ^266@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:267@ CHECK-ERRORS: svc #256268@ CHECK-ERRORS: ^269@ CHECK-ERRORS: note: instruction requires: arm-mode270@ CHECK-ERRORS: note: operand must be an immediate in the range [0,255]271 272 273@ Out of range immediate for ADD SP instructions274 add sp, #-1275 add sp, #3276 add sp, sp, #512277 add r2, sp, #1024278@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:279@ CHECK-ERRORS: add sp, #-1280@ CHECK-ERRORS: ^281@ CHECK-ERRORS: note: instruction requires: thumb2282@ CHECK-ERRORS: add sp, #-1283@ CHECK-ERRORS: ^284@ CHECK-ERRORS: note: operand must be a register in range [r0, r15]285@ CHECK-ERRORS: add sp, #-1286@ CHECK-ERRORS: ^287@ CHECK-ERRORS: note: invalid operand for instruction288@ CHECK-ERRORS: add sp, #-1289@ CHECK-ERRORS: ^290@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:291@ CHECK-ERRORS: add sp, #3292@ CHECK-ERRORS: ^293@ CHECK-ERRORS: note: instruction requires: thumb2294@ CHECK-ERRORS: add sp, #3295@ CHECK-ERRORS: ^296@ CHECK-ERRORS: note: operand must be a register in range [r0, r15]297@ CHECK-ERRORS: add sp, #3298@ CHECK-ERRORS: ^299@ CHECK-ERRORS: note: invalid operand for instruction300@ CHECK-ERRORS: add sp, #3301@ CHECK-ERRORS: ^302@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:303@ CHECK-ERRORS: add sp, sp, #512304@ CHECK-ERRORS: ^305@ CHECK-ERRORS: note: instruction requires: thumb2306@ CHECK-ERRORS: add sp, sp, #512307@ CHECK-ERRORS: ^308@ CHECK-ERRORS: note: operand must be a register in range [r0, r15]309@ CHECK-ERRORS: add sp, sp, #512310@ CHECK-ERRORS: ^311@ CHECK-ERRORS: note: invalid operand for instruction312@ CHECK-ERRORS: add sp, sp, #512313@ CHECK-ERRORS: ^314@ CHECK-ERRORS: note: instruction requires: thumb2315@ CHECK-ERRORS: add r2, sp, #1024316@ CHECK-ERRORS: ^317 add r2, sp, ip318@ CHECK-ERRORS: error: source register must be the same as destination319@ CHECK-ERRORS: add r2, sp, ip320@ CHECK-ERRORS: ^321 322 323@------------------------------------------------------------------------------324@ B/Bcc - out of range immediates for Thumb1 branches325@------------------------------------------------------------------------------326 327 beq #-258328 bne #256329 bgt #13330 b #-1048578331 b #1048576332 b #10323333 334@ CHECK-ERRORS: error: branch target out of range335@ CHECK-ERRORS: error: branch target out of range336@ CHECK-ERRORS: error: branch target out of range337@ CHECK-ERRORS: error: branch target out of range338@ CHECK-ERRORS: error: branch target out of range339@ CHECK-ERRORS: error: branch target out of range340 341@------------------------------------------------------------------------------342@ CBZ/CBNZ - out of range immediates for branches343@------------------------------------------------------------------------------344 345 cbz r0, #-2346 cbz r0, #0347 cbz r0, #17348 cbnz r0, #126349 cbnz r0, #128350 351@ CHECK-ERRORS-V7M: error: branch target out of range352@ CHECK-ERRORS-V7M: error: invalid operand for instruction353@ CHECK-ERRORS-V7M: error: branch target out of range354@ CHECK-ERRORS-V8: error: branch target out of range355@ CHECK-ERRORS-V8: error: invalid operand for instruction356@ CHECK-ERRORS-V8: error: branch target out of range357 358@------------------------------------------------------------------------------359@ SEV/WFE/WFI/YIELD - are not supported pre v6M or v6T2360@------------------------------------------------------------------------------361 sev362 wfe363 wfi364 yield365 366@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2367@ CHECK-ERRORS: sev368@ CHECK-ERRORS: ^369@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2370@ CHECK-ERRORS: wfe371@ CHECK-ERRORS: ^372@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2373@ CHECK-ERRORS: wfi374@ CHECK-ERRORS: ^375@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2376@ CHECK-ERRORS: yield377@ CHECK-ERRORS: ^378 379@------------------------------------------------------------------------------380@ PLDW required mp-extensions381@------------------------------------------------------------------------------382 pldw [r0, #4]383@ CHECK-ERRORS: error: instruction requires: mp-extensions384 385@------------------------------------------------------------------------------386@ LDR(lit) - invalid offsets387@------------------------------------------------------------------------------388 389 ldr r4, [pc, #-12]390@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:391@ CHECK-ERRORS: note: instruction requires: thumb2392@ CHECK-ERRORS: note: instruction requires: arm-mode393@ CHECK-ERRORS: note: invalid operand for instruction394 395@------------------------------------------------------------------------------396@ STC2{L}/LDC2{L} - requires thumb2397@------------------------------------------------------------------------------398 stc2 p0, c8, [r1, #4]399 stc2l p6, c2, [r7, #4]400 ldc2 p0, c8, [r1, #4]401 ldc2l p6, c2, [r7, #4]402@ CHECK-ERRORS: error: invalid instruction403@ CHECK-ERRORS: error: invalid instruction404@ CHECK-ERRORS: error: invalid instruction405@ CHECK-ERRORS: error: invalid instruction406 407@------------------------------------------------------------------------------408@ Generic error for too few operands409@------------------------------------------------------------------------------410 411 adds412 adds r0413@ CHECK-ERRORS: error: too few operands for instruction414@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:415@ CHECK-ERRORS: note: too few operands for instruction416 417@------------------------------------------------------------------------------418@ Out of range width for SBFX/UBFX419@------------------------------------------------------------------------------420 421 sbfx r4, r5, #31, #2422 ubfx r4, r5, #16, #17423 424@ CHECK-ERRORS-V8: error: bitfield width must be in range [1,32-lsb]425@ CHECK-ERRORS-V8: sbfx r4, r5, #31, #2426@ CHECK-ERRORS-V8: ^427@ CHECK-ERRORS-V8: error: bitfield width must be in range [1,32-lsb]428@ CHECK-ERRORS-V8: ubfx r4, r5, #16, #17429@ CHECK-ERRORS-V8: ^430 431@------------------------------------------------------------------------------432@ Writeback store writing to same register as value433@------------------------------------------------------------------------------434 435 str r0, [r0, #4]!436 str r0, [r0], #4437 strh r0, [r0, #2]!438 strh r0, [r0], #2439 strb r0, [r0, #1]!440 strb r0, [r0], #1441 strd r0, r1, [r0], #1442 strd r1, r0, [r0], #1443@ CHECK-ERRORS-V8: error: source register and base register can't be identical444@ CHECK-ERRORS-V8: str r0, [r0, #4]!445@ CHECK-ERRORS-V8: ^446@ CHECK-ERRORS-V8: error: source register and base register can't be identical447@ CHECK-ERRORS-V8: str r0, [r0], #4448@ CHECK-ERRORS-V8: ^449@ CHECK-ERRORS-V8: error: source register and base register can't be identical450@ CHECK-ERRORS-V8: strh r0, [r0, #2]!451@ CHECK-ERRORS-V8: ^452@ CHECK-ERRORS-V8: error: source register and base register can't be identical453@ CHECK-ERRORS-V8: strh r0, [r0], #2454@ CHECK-ERRORS-V8: ^455@ CHECK-ERRORS-V8: error: source register and base register can't be identical456@ CHECK-ERRORS-V8: strb r0, [r0, #1]!457@ CHECK-ERRORS-V8: ^458@ CHECK-ERRORS-V8: error: source register and base register can't be identical459@ CHECK-ERRORS-V8: strb r0, [r0], #1460@ CHECK-ERRORS-V8: ^461@ CHECK-ERRORS-V8: error: source register and base register can't be identical462@ CHECK-ERRORS-V8: strd r0, r1, [r0], #1463@ CHECK-ERRORS-V8: ^464@ CHECK-ERRORS-V8: error: source register and base register can't be identical465@ CHECK-ERRORS-V8: strd r1, r0, [r0], #1466@ CHECK-ERRORS-V8: ^467