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1@ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t2@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s3 4@ RUN: not llvm-mc -triple=thumbv8-apple-darwin < %s 2> %t5@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s6 7@ Ill-formed IT block instructions.8 itet eq9 addle r0, r1, r210 nop11 it le12 iteeee gt13 ittfe le14 nopeq15 16@ CHECK-ERRORS: error: incorrect condition in IT block; got 'le', but expected 'eq'17@ CHECK-ERRORS: addle r0, r1, r218@ CHECK-ERRORS: ^19@ CHECK-ERRORS: error: incorrect condition in IT block; got 'al', but expected 'ne'20@ CHECK-ERRORS: nop21@ CHECK-ERRORS: ^22@ CHECK-ERRORS: error: instructions in IT block must be predicable23@ CHECK-ERRORS: it le24@ CHECK-ERRORS: ^25@ CHECK-ERRORS: error: too many conditions on IT instruction26@ CHECK-ERRORS: iteeee gt27@ CHECK-ERRORS: ^28@ CHECK-ERRORS: error: illegal IT block condition mask 'tfe'29@ CHECK-ERRORS: ittfe le30@ CHECK-ERRORS: ^31@ CHECK-ERRORS: error: predicated instructions must be in IT block32@ CHECK-ERRORS: nopeq33@ CHECK-ERRORS: ^34 35 @ Out of range immediates for MRC/MRC2/MRRC/MRRC236 mrc p14, #8, r1, c1, c2, #437 mrc p14, #1, r1, c1, c2, #838 mrc2 p14, #8, r1, c1, c2, #439 mrc2 p14, #0, r1, c1, c2, #940 mrrc p14, #16, r5, r4, c141 mrrc2 p14, #17, r5, r4, c142@ CHECK-ERRORS: operand must be an immediate in the range [0,7]43@ CHECK-ERRORS: operand must be an immediate in the range [0,7]44@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]45@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]46@ CHECK-ERRORS-V8: invalid instruction47@ CHECK-ERRORS-V8: too many operands for instruction48@ CHECK-ERRORS: operand must be an immediate in the range [0,15]49@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]50@ CHECK-ERRORS-V8: invalid instruction51 52 @ Out of range immediate for ROR.53 @ (Assembling this instruction to "mov r1, r1" might also be OK.)54 ror r1, r1, #055@ CHECK-ERRORS: invalid instruction56@ CHECK-ERRORS: operand must be an immediate in the range [1,31]57 58 isb #-159 isb #1660@ CHECK-ERRORS: error: immediate value out of range61@ CHECK-ERRORS: error: immediate value out of range62 63 itt eq64 bkpteq #165@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified66 67 nopeq68 nopeq69 70@ out of range operands for Thumb2 targets71 72 beq.w #-104857873 bne.w #104857674 blt.w #101341175 b.w #-1677721876 b.w #1677721677 b.w #159231378 79@ CHECK-ERRORS: error: branch target out of range80@ CHECK-ERRORS: error: branch target out of range81@ CHECK-ERRORS: error: branch target out of range82@ CHECK-ERRORS: error: branch target out of range83@ CHECK-ERRORS: error: branch target out of range84@ CHECK-ERRORS: error: branch target out of range85 86foo2:87 movw r0, foo288 movt r0, foo289 movt r0, #0x1000090 movt r0, #0x1000091@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper1692@ CHECK-ERRORS: ^93@ CHECK-ERRORS: immediate expression for mov requires :lower16: or :upper1694@ CHECK-ERRORS: ^95@ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression96@ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression97 98 and sp, r1, #8000800099 and pc, r1, #80008000100@ CHECK-ERRORS: error: invalid instruction101@ CHECK-ERRORS: error: invalid instruction102 103 ssat r0, #1, r0, asr #32104 usat r0, #1, r0, asr #32105@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode106@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode107 108 @ PC is not valid as shifted-rGPR109 sbc.w r2, r7, pc, lsr #16110 and.w r2, r7, pc, lsr #16111@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:112@ CHECK-ERRORS: note: invalid operand for instruction113@ CHECK-ERRORS-V7: note: operand must be a register in range [r0, r12] or r14114@ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14]115@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:116@ CHECK-ERRORS: note: invalid operand for instruction117@ CHECK-ERRORS-V7: note: operand must be a register in range [r0, r12] or r14118@ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14]119 120 121 @ PC is not valid as base of load122 ldr r0, [pc, r0]123 ldrb r1, [pc, r2]124 ldrh r3, [pc, r3]125 pld r4, [pc, r5]126 str r6, [pc, r7]127 strb r7 [pc, r8]128 strh r9, [pc, r10]129@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:130@ CHECK-ERRORS: note: invalid operand for instruction131@ CHECK-ERRORS: note: instruction requires: arm-mode132@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:133@ CHECK-ERRORS: note: invalid operand for instruction134@ CHECK-ERRORS: note: instruction requires: arm-mode135@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:136@ CHECK-ERRORS: note: instruction requires: arm-mode137@ CHECK-ERRORS: note: invalid operand for instruction138@ CHECK-ERRORS: error: invalid instruction139@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:140@ CHECK-ERRORS: note: invalid operand for instruction141@ CHECK-ERRORS: note: instruction requires: arm-mode142@ CHECK-ERRORS: error: immediate value expected for vector index143@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:144@ CHECK-ERRORS: note: instruction requires: arm-mode145@ CHECK-ERRORS: note: invalid operand for instruction146 147 @ SWP(B) is an ARM-only instruction148 swp r0, r1, [r2]149 swpb r3, r4, [r5]150@ CHECK-ERRORS-V7: error: instruction requires: arm-mode151@ CHECK-ERRORS-V7: error: instruction requires: arm-mode152@ CHECK-ERRORS-V8: error: invalid instruction153@ CHECK-ERRORS-V8: error: invalid instruction154 155 @ Generic error for too few operands156 adds157 adds r0158@ CHECK-ERRORS: error: too few operands for instruction159@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:160@ CHECK-ERRORS: note: too few operands for instruction161@ CHECK-ERRORS: note: operand must be a register in range [r0, r15]162 163 tst sp, #3164 tst sp, r5165 tst sp, r5, lsl #3166@ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14167@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14168@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14169 170 teq sp, #5171 teq sp, r7172 teq sp, r9, lsl #2173@ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14174@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14175@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14176 177 tbb [r0, sp]178 @ v8 allows rm = sp179@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later180 tbb [r0, pc]181 @ rm = pc is always unpredictable182@ CHECK-ERRORS: error: invalid operand for instruction183 tbb [sp, r0]184 @ v8 allows rn = sp185@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later186 @ rn = pc is allowed so not included here187 188 tbh [r0, sp, lsl #1]189 @ v8 allows rm = sp190@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later191 tbh [r0, pc, lsl #1]192 @ rm = pc is always unpredictable193@ CHECK-ERRORS: error: invalid operand for instruction194 tbh [sp, r0, lsl #1]195 @ v8 allows rn = sp196@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later197 @ rn=pc is allowed so not included here198