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1// RUN: not llvm-mc -triple=thumbv8m.base -show-encoding < %s 2>%t \2// RUN: | FileCheck --check-prefix=CHECK %s3// RUN: FileCheck --check-prefixes=UNDEF-BASELINE,UNDEF < %t %s4// RUN: not llvm-mc -triple=thumbv8m.main -show-encoding < %s 2>%t \5// RUN: | FileCheck --check-prefixes=CHECK-MAINLINE,CHECK %s6// RUN: FileCheck --check-prefixes=UNDEF-MAINLINE,UNDEF < %t %s7// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+dsp -show-encoding < %s 2>%t \8// RUN: | FileCheck --check-prefixes=CHECK-MAINLINE_DSP,CHECK %s9// RUN: FileCheck --check-prefixes=UNDEF-MAINLINE_DSP,UNDEF < %t %s10 11// Simple check that baseline is v6M and mainline is v7M12// UNDEF-BASELINE: error: instruction requires: thumb213// UNDEF-MAINLINE-NOT: error: instruction requires:14// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:15mov.w r0, r016 17// Check that .arm is invalid18// UNDEF: target does not support ARM mode19.arm20 21// And only +dsp has DSP and instructions22// UNDEF-BASELINE: error: instruction requires: dsp thumb223// UNDEF-MAINLINE: error: instruction requires: dsp24// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:25qadd16 r0, r0, r026// UNDEF-BASELINE: error: instruction requires: dsp thumb227// UNDEF-MAINLINE: error: instruction requires: dsp28// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:29uxtab16 r0, r1, r230 31// Instruction availibility checks32 33// 'Barrier instructions'34 35// CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]36isb sy37 38// 'Code optimization'39 40// CHECK: cbz r3, .Ltmp0 @ encoding: [0x03'A',0xb1'A']41// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb42cbz r3, 1f43 44// CHECK: cbnz r3, .Ltmp0 @ encoding: [0x03'A',0xb9'A']45// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb46cbnz r3, 1f47 48// CHECK: b.w .Ltmp0 @ encoding: [A,0xf0'A',A,0x90'A']49// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_t2_uncondbranch50b.w 1f51 52// CHECK: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]53sdiv r1, r2, r354 55// CHECK: udiv r1, r2, r3 @ encoding: [0xb2,0xfb,0xf3,0xf1]56udiv r1, r2, r357 58// 'Exclusives from ARMv7-M'59 60// CHECK: clrex @ encoding: [0xbf,0xf3,0x2f,0x8f]61clrex62 63// CHECK: ldrex r1, [r2, #4] @ encoding: [0x52,0xe8,0x01,0x1f]64ldrex r1, [r2, #4]65 66// CHECK: ldrexb r1, [r2] @ encoding: [0xd2,0xe8,0x4f,0x1f]67ldrexb r1, [r2]68 69// CHECK: ldrexh r1, [r2] @ encoding: [0xd2,0xe8,0x5f,0x1f]70ldrexh r1, [r2]71 72// UNDEF-BASELINE: error: instruction requires: !armv*m thumb273// UNDEF-MAINLINE: error: instruction requires: !armv*m74ldrexd r0, r1, [r2]75 76// CHECK: strex r1, r2, [r3, #4] @ encoding: [0x43,0xe8,0x01,0x21]77strex r1, r2, [r3, #4]78 79// CHECK: strexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0x41,0x2f]80strexb r1, r2, [r3]81 82// CHECK: strexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0x51,0x2f]83strexh r1, r2, [r3]84 85// UNDEF-BASELINE: error: instruction requires: !armv*m thumb286// UNDEF-MAINLINE: error: instruction requires: !armv*m87strexd r0, r1, r2, [r3]88 89// 'XO generation'90 91// CHECK: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]92movw r1, #0xffff93 94// CHECK: movt r1, #65535 @ encoding: [0xcf,0xf6,0xff,0x71]95movt r1, #0xffff96 97// 'Acquire/Release from ARMv8-A'98 99// CHECK: lda r1, [r2] @ encoding: [0xd2,0xe8,0xaf,0x1f]100lda r1, [r2]101 102// CHECK: ldab r1, [r2] @ encoding: [0xd2,0xe8,0x8f,0x1f]103ldab r1, [r2]104 105// CHECK: ldah r1, [r2] @ encoding: [0xd2,0xe8,0x9f,0x1f]106ldah r1, [r2]107 108// CHECK: stl r1, [r3] @ encoding: [0xc3,0xe8,0xaf,0x1f]109stl r1, [r3]110 111// CHECK: stlb r1, [r3] @ encoding: [0xc3,0xe8,0x8f,0x1f]112stlb r1, [r3]113 114// CHECK: stlh r1, [r3] @ encoding: [0xc3,0xe8,0x9f,0x1f]115stlh r1, [r3]116 117// CHECK: ldaex r1, [r2] @ encoding: [0xd2,0xe8,0xef,0x1f]118ldaex r1, [r2]119 120// CHECK: ldaexb r1, [r2] @ encoding: [0xd2,0xe8,0xcf,0x1f]121ldaexb r1, [r2]122 123// CHECK: ldaexh r1, [r2] @ encoding: [0xd2,0xe8,0xdf,0x1f]124ldaexh r1, [r2]125 126// UNDEF: error: instruction requires: !armv*m127ldaexd r0, r1, [r2]128 129// CHECK: stlex r1, r2, [r3] @ encoding: [0xc3,0xe8,0xe1,0x2f]130stlex r1, r2, [r3]131 132// CHECK: stlexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0xc1,0x2f]133stlexb r1, r2, [r3]134 135// CHECK: stlexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0xd1,0x2f]136stlexh r1, r2, [r3]137 138// UNDEF: error: instruction requires: !armv*m139stlexd r0, r1, r2, [r2]140 141// ARMv8-M Security Extensions142 143// CHECK: sg @ encoding: [0x7f,0xe9,0x7f,0xe9]144sg145 146// CHECK: bxns r0 @ encoding: [0x04,0x47]147bxns r0148 149// UNDEF-BASELINE: error: invalid instruction150// UNDEF-BASELINE: error: conditional execution not supported in Thumb1151// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]152// CHECK-MAINLINE: bxnseq r1 @ encoding: [0x0c,0x47]153it eq154bxnseq r1155 156// CHECK: bxns lr @ encoding: [0x74,0x47]157bxns lr158 159// CHECK: blxns r0 @ encoding: [0x84,0x47]160blxns r0161 162// UNDEF-BASELINE: error: invalid instruction163// UNDEF-BASELINE: error: conditional execution not supported in Thumb1164// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]165// CHECK-MAINLINE: blxnseq r1 @ encoding: [0x8c,0x47]166it eq167blxnseq r1168 169// CHECK: tt r0, r1 @ encoding: [0x41,0xe8,0x00,0xf0]170tt r0, r1171 172// CHECK: tt r0, sp @ encoding: [0x4d,0xe8,0x00,0xf0]173tt r0, sp174 175// CHECK: tta r0, r1 @ encoding: [0x41,0xe8,0x80,0xf0]176tta r0, r1177 178// CHECK: ttt r0, r1 @ encoding: [0x41,0xe8,0x40,0xf0]179ttt r0, r1180 181// CHECK: ttat r0, r1 @ encoding: [0x41,0xe8,0xc0,0xf0]182ttat r0, r1183 184// 'Lazy Load/Store Multiple'185 186// UNDEF-BASELINE: error: instruction requires: armv8m.main187// CHECK-MAINLINE: vlldm r5, {d0 - d15} @ encoding: [0x35,0xec,0x00,0x0a]188// CHECK-MAINLINE_DSP: vlldm r5, {d0 - d15} @ encoding: [0x35,0xec,0x00,0x0a]189vlldm r5190 191// UNDEF-BASELINE: error: instruction requires: armv8m.main192// CHECK-MAINLINE: vlstm r10, {d0 - d15} @ encoding: [0x2a,0xec,0x00,0x0a]193// CHECK-MAINLINE_DSP: vlstm r10, {d0 - d15} @ encoding: [0x2a,0xec,0x00,0x0a]194vlstm r10195 196// New SYSm's197 198MRS r1, MSP_NS199// CHECK: mrs r1, msp_ns @ encoding: [0xef,0xf3,0x88,0x81]200MSR PSP_NS, r2201// CHECK: msr psp_ns, r2 @ encoding: [0x82,0xf3,0x89,0x88]202MRS r3, PRIMASK_NS203// CHECK: mrs r3, primask_ns @ encoding: [0xef,0xf3,0x90,0x83]204MSR CONTROL_NS, r4205// CHECK: msr control_ns, r4 @ encoding: [0x84,0xf3,0x94,0x88]206MRS r5, SP_NS207// CHECK: mrs r5, sp_ns @ encoding: [0xef,0xf3,0x98,0x85]208MRS r6,MSPLIM209// CHECK: mrs r6, msplim @ encoding: [0xef,0xf3,0x0a,0x86]210MRS r7,PSPLIM211// CHECK: mrs r7, psplim @ encoding: [0xef,0xf3,0x0b,0x87]212MSR MSPLIM,r8213// CHECK: msr msplim, r8 @ encoding: [0x88,0xf3,0x0a,0x88]214MSR PSPLIM,r9215// CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88]216 217MRS r10, MSPLIM_NS218// CHECK: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]219MSR PSPLIM_NS, r11220// CHECK: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]221MRS r12, BASEPRI_NS222// CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c]223// UNDEF-BASELINE: error: invalid operand for instruction224MSR FAULTMASK_NS, r14225// CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]226// UNDEF-BASELINE: error: invalid operand for instruction227 228// Unpredictable SYSm's229MRS r8, 146230// CHECK: mrs r8, 146 @ encoding: [0xef,0xf3,0x92,0x88]231MSR 146, r8232// CHECK: msr 146, r8 @ encoding: [0x88,0xf3,0x92,0x80]233 234// Invalid operand tests235// UNDEF: error: too many operands for instruction236// UNDEF: sg #0237sg #0238// UNDEF: error: too many operands for instruction239// UNDEF: sg r0240sg r0241// UNDEF: error: too many operands for instruction242// UNDEF: bxns r0, r1243bxns r0, r1244// UNDEF: error: too many operands for instruction245// UNDEF: blxns r0, #0246blxns r0, #0247// UNDEF: error: operand must be a register in range [r0, r14]248// UNDEF: blxns label249blxns label250// UNDEF: error: too many operands for instruction251// UNDEF: tt r0, r1, r2252tt r0, r1, r2253// UNDEF: error: operand must be a register in range [r0, r14]254// UNDEF: tt r0, [r1]255tt r0, [r1]256// UNDEF: error: too many operands for instruction257// UNDEF: tt r0, r1, #4258tt r0, r1, #4259// UNDEF: error: operand must be a register in range [r0, r14]260// UNDEF: tt r0, #4261tt r0, #4262 263// Unpredictable operands264// UNDEF: error: operand must be a register in range [r0, r14]265// UNDEF: blxns pc266blxns pc267// UNDEF: error: operand must be a register in range [r0, r12] or r14268// UNDEF: tt sp, r0269tt sp, r0270// UNDEF: error: operand must be a register in range [r0, r12] or r14271// UNDEF: tt pc, r0272tt pc, r0273// UNDEF: error: operand must be a register in range [r0, r14]274// UNDEF: tt r0, pc275tt r0, pc276 277// UNDEF-BASELINE: error: invalid instruction278// UNDEF-MAINLINE: error: operand must be a register in range [r0, r14]279// UNDEF: vlldm pc280vlldm pc281 282// UNDEF-BASELINE: error: invalid instruction283// UNDEF-MAINLINE: error: operand must be a register in range [r0, r14]284// UNDEF: vlstm pc285vlstm pc286