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1// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding < %s 2>%t \2// RUN: | FileCheck --check-prefix=CHECK %s3// RUN:   FileCheck --check-prefix=ERROR < %t %s4// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding < %s 2>%t \5// RUN: | FileCheck --check-prefix=CHECK %s6// RUN:   FileCheck --check-prefix=ERROR < %t %s7// RUN: not llvm-mc -triple=thumbv8.1m.main-none-none-eabi -mattr=-8msecext < %s 2>%t8// RUN: FileCheck --check-prefix=NOSEC < %t %s9 10// CHECK: vscclrm            {s0, s1, s2, s3, vpr} @ encoding: [0x9f,0xec,0x04,0x0a]11// NOSEC: instruction requires: ARMv8-M Security Extensions12vscclrm {s0-s3, vpr}13 14// CHECK: vscclrm            {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]15// NOSEC: instruction requires: ARMv8-M Security Extensions16vscclrm {s3-s8, vpr}17 18// CHECK: vscclrm            {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr} @ encoding: [0x9f,0xec,0x0c,0x9a]19vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}20 21// CHECK: vscclrm            {s31, vpr} @ encoding: [0xdf,0xec,0x01,0xfa]22vscclrm {s31, vpr}23 24// CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]25vscclrm {d0-d1, vpr}26 27// CHECK: vscclrm            {d0, d1, d2, d3, vpr}  @ encoding: [0x9f,0xec,0x08,0x0b]28vscclrm {d0-d3, vpr}29 30// CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]31vscclrm {d5-d7, vpr}32 33// CHECK: it                 hi @ encoding: [0x88,0xbf]34it hi35// CHECK: vscclrmhi          {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} @ encoding: [0xdf,0xec,0x1d,0x1a]36vscclrmhi {s3-s31, vpr}37 38// CHECK: vscclrm            {vpr} @ encoding: [0x9f,0xec,0x00,0x0a]39vscclrm {vpr}40 41// CHECK: vscclrm            {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0b]42vscclrm {d0-d31, vpr}43 44// CHECK: vscclrm            {d31, vpr} @ encoding: [0xdf,0xec,0x02,0xfb]45vscclrm {d31, vpr}46 47// CHECK: vscclrm            {s31, d16, vpr} @ encoding: [0xdf,0xec,0x03,0xfa]48vscclrm {s31, d16, vpr}49 50// CHECK: vscclrm            {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0a]51vscclrm {s0-s31, d16-d31, vpr}52 53// CHECK: vscclrm            {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0a]54vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr}55 56// ERROR: non-contiguous register range57vscclrm {s0, s3-s4, vpr}58 59// ERROR: non-contiguous register range60vscclrm {s31, d16, s30, vpr}61 62// ERROR: register expected63vscclrm {s32, vpr}64 65// ERROR: register expected66vscclrm {d32, vpr}67 68// ERROR: register expected69vscclrm {s31-s32, vpr}70 71// ERROR: register expected72vscclrm {d31-d32, vpr}73 74// ERROR: invalid operand for instruction75vscclrm {s0-s1}76 77// ERROR: register list not in ascending order78vscclrm {vpr, s0}79 80// ERROR: register list not in ascending order81vscclrm {vpr, s31}82 83// ERROR: register list not in ascending order84vscclrm {vpr, d0}85 86// ERROR: register list not in ascending order87vscclrm {vpr, d31}88 89// ERROR: invalid register in register list90vscclrm {s0, d0, vpr}91 92// ERROR: invalid register in register list93vscclrm {s0, d1, vpr}94 95// ERROR: invalid register in register list96vscclrm {d16, s31, vpr}97