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1# RUN: not llvm-mc -disassemble -triple=aarch64 %s 2> %t2# RUN: FileCheck %s < %t3# RUN: not llvm-mc -disassemble -triple=arm64 %s 2> %t4# RUN: FileCheck %s < %t5 6# Instructions notionally in the add/sub (extended register) sheet, but with7# invalid shift amount or "opt" field.8[0x00 0x10 0xa0 0x0b]9[0x00 0x10 0x60 0x0b]10[0x00 0x14 0x20 0x0b]11# CHECK: invalid instruction encoding12# CHECK: invalid instruction encoding13# CHECK: invalid instruction encoding14 15# Instructions notionally in the add/sub (immediate) sheet, but with16# invalid "shift" field.17[0xdf 0x3 0x80 0x91]18[0xed 0x8e 0xc4 0x31]19[0x62 0xfc 0xbf 0x11]20[0x3 0xff 0xff 0x91]21# CHECK: invalid instruction encoding22# CHECK: invalid instruction encoding23# CHECK: invalid instruction encoding24# CHECK: invalid instruction encoding25 26# Instructions notionally in the load/store (unsigned immediate) sheet.27# Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b1128[0xd7 0xfc 0xff 0xb9]29[0xd7 0xfc 0xcf 0xf9]30# CHECK: invalid instruction encoding31# CHECK: invalid instruction encoding32 33# Instructions notionally in the floating-point <-> fixed-point conversion34# Scale field is 64-<imm> and <imm> should be 1-32 for a 32-bit int register.35[0x23 0x01 0x18 0x1e]36[0x23 0x25 0x42 0x1e]37# CHECK: invalid instruction encoding38# CHECK: invalid instruction encoding39 40# Instructions notionally in the logical (shifted register) sheet, but with out41# of range shift: w-registers can only have 0-31.42[0x00 0x80 0x00 0x0a]43# CHECK: invalid instruction encoding44 45# Instructions notionally in the move wide (immediate) sheet, but with out46# of range shift: w-registers can only have 0 or 16.47[0x00 0x00 0xc0 0x12]48[0x12 0x34 0xe0 0x52]49# CHECK: invalid instruction encoding50# CHECK: invalid instruction encoding51 52# Data-processing instructions are undefined when S=1 and for the 0b000011153# value in opcode:sf54[0x00 0x00 0xc0 0x5f]55[0x56 0x0c 0xc0 0x5a]56# CHECK: invalid instruction encoding57# CHECK: invalid instruction encoding58 59# Data-processing instructions (2 source) are undefined for a value of60# 0001xx:0:x or 0011xx:0:x for opcode:S:sf61[0x00 0x30 0xc1 0x1a]62[0x00 0x10 0xc1 0x1a]63# CHECK: invalid instruction encoding64# CHECK: invalid instruction encoding65 66 67