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1# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s2# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s3 40x8 0xcc 0x38 0xd55# CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}}60x1a 0xc8 0x38 0xd57# CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}}80x42 0xcc 0x38 0xd59# CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}}100x51 0xc8 0x38 0xd511# CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}}120x7d 0xcb 0x38 0xd513# CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}}140x24 0xcb 0x3c 0xd515# CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}}160x78 0xcb 0x3c 0xd517# CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}}180xa9 0xcb 0x3c 0xd519# CHECK: mrs x9, {{ich_elrsr_el2|ICH_ELRSR_EL2}}200x78 0xcc 0x38 0xd521# CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}}220x6e 0xc8 0x38 0xd523# CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}}240x13 0x46 0x38 0xd525# CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}}260x97 0xcc 0x38 0xd527# CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}}280x94 0xcc 0x3e 0xd529# CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}}300xbc 0xcc 0x38 0xd531# CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}}320xb9 0xc9 0x3c 0xd533# CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}}340xa8 0xcc 0x3e 0xd535# CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}}360xd6 0xcc 0x38 0xd537# CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}380xe5 0xcc 0x38 0xd539# CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}400xe7 0xcc 0x3e 0xd541# CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}420x84 0xc8 0x38 0xd543# CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}}440xab 0xc8 0x38 0xd545# CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}}460xdb 0xc8 0x38 0xd547# CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}}480xf5 0xc8 0x38 0xd549# CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}}500x2 0xc9 0x38 0xd551# CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}}520x35 0xc9 0x38 0xd553# CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}}540x4a 0xc9 0x38 0xd555# CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}}560x7b 0xc9 0x38 0xd557# CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}}580x14 0xc8 0x3c 0xd559# CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}}600x35 0xc8 0x3c 0xd561# CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}}620x45 0xc8 0x3c 0xd563# CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}}640x64 0xc8 0x3c 0xd565# CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}}660xf 0xc9 0x3c 0xd567# CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}}680x2c 0xc9 0x3c 0xd569# CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}}700x5b 0xc9 0x3c 0xd571# CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}}720x74 0xc9 0x3c 0xd573# CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}}740xa 0xcb 0x3c 0xd575# CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}}760x5b 0xcb 0x3c 0xd577# CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}}780xe6 0xcb 0x3c 0xd579# CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}}800x3 0xcc 0x3c 0xd581# CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}}820x21 0xcc 0x3c 0xd583# CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}}840x56 0xcc 0x3c 0xd585# CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}}860x75 0xcc 0x3c 0xd587# CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}}880x86 0xcc 0x3c 0xd589# CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}}900xaa 0xcc 0x3c 0xd591# CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}}920xcb 0xcc 0x3c 0xd593# CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}}940xec 0xcc 0x3c 0xd595# CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}}960x0 0xcd 0x3c 0xd597# CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}}980x35 0xcd 0x3c 0xd599# CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}}1000x4d 0xcd 0x3c 0xd5101# CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}}1020x7a 0xcd 0x3c 0xd5103# CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}}1040x81 0xcd 0x3c 0xd5105# CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}}1060xa8 0xcd 0x3c 0xd5107# CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}}1080xc2 0xcd 0x3c 0xd5109# CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}}1100xe8 0xcd 0x3c 0xd5111# CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}}1120x3b 0xcc 0x18 0xd5113# CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x271140x25 0xc8 0x18 0xd5115# CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x51160x2d 0xcb 0x18 0xd5117# CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x131180xb5 0xcb 0x18 0xd5119# CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x211200xd9 0xcb 0x18 0xd5121# CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x251220xfc 0xcb 0x18 0xd5123# CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x281240x67 0xcc 0x18 0xd5125# CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x71260x69 0xc8 0x18 0xd5127# CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x91280x1d 0x46 0x18 0xd5129# CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x291300x98 0xcc 0x18 0xd5131# CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x241320x80 0xcc 0x1e 0xd5133# CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x01340xa2 0xcc 0x18 0xd5135# CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x21360xa5 0xc9 0x1c 0xd5137# CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x51380xaa 0xcc 0x1e 0xd5139# CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x101400xd6 0xcc 0x18 0xd5141# CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x221420xeb 0xcc 0x18 0xd5143# CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x111440xe8 0xcc 0x1e 0xd5145# CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x81460x9b 0xc8 0x18 0xd5147# CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x271480xa5 0xc8 0x18 0xd5149# CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x51500xd4 0xc8 0x18 0xd5151# CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x201520xe0 0xc8 0x18 0xd5153# CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x01540x2 0xc9 0x18 0xd5155# CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x21560x3d 0xc9 0x18 0xd5157# CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x291580x57 0xc9 0x18 0xd5159# CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x231600x6b 0xc9 0x18 0xd5161# CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x111620x2 0xc8 0x1c 0xd5163# CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x21640x3b 0xc8 0x1c 0xd5165# CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x271660x47 0xc8 0x1c 0xd5167# CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x71680x61 0xc8 0x1c 0xd5169# CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x11700x7 0xc9 0x1c 0xd5171# CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x71720x2c 0xc9 0x1c 0xd5173# CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x121740x4e 0xc9 0x1c 0xd5175# CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x141760x6d 0xc9 0x1c 0xd5177# CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x131780x1 0xcb 0x1c 0xd5179# CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x11800x4a 0xcb 0x1c 0xd5181# CHECK: msr S3_4_C12_C11_2, x101820xf8 0xcb 0x1c 0xd5183# CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x241840x1a 0xcc 0x1c 0xd5185# CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x261860x29 0xcc 0x1c 0xd5187# CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x91880x52 0xcc 0x1c 0xd5189# CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x181900x7a 0xcc 0x1c 0xd5191# CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x261920x96 0xcc 0x1c 0xd5193# CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x221940xba 0xcc 0x1c 0xd5195# CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x261960xdb 0xcc 0x1c 0xd5197# CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x271980xe8 0xcc 0x1c 0xd5199# CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x82000x11 0xcd 0x1c 0xd5201# CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x172020x33 0xcd 0x1c 0xd5203# CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x192040x51 0xcd 0x1c 0xd5205# CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x172060x65 0xcd 0x1c 0xd5207# CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x52080x9d 0xcd 0x1c 0xd5209# CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x292100xa2 0xcd 0x1c 0xd5211# CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x22120xcd 0xcd 0x1c 0xd5213# CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x132140xfb 0xcd 0x1c 0xd5215# CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27216