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1# RUN: llvm-mc -triple=arc -disassemble %s | FileCheck %s2 3# CHECK: ld %r0, [%r0,0]40x00 0x10 0x00 0x005 6# CHECK: ldh %r0, [%r0,0]70x00 0x10 0x00 0x018 9# CHECK: ldb %r0, [%r0,0]100x00 0x10 0x80 0x0011 12# CHECK: ld %r1, [%r0,12]130x0c 0x10 0x01 0x0014 15# CHECK: ld %r14, [%fp,-12]160xf4 0x13 0x0e 0xb017 18# CHECK: ld %r3, [%r0,-12]190xf4 0x10 0x03 0x8020 21# CHECK: ld %r0, [%r0,244]220xf4 0x10 0x00 0x0023 24# CHECK: ld %r0, [%r0,-12]250xf4 0x10 0x00 0x8026 27# CHECK: ldh.x %r3, [%r1,0]280x00 0x11 0x43 0x0129 30# CHECK: ldh.x %r2, [%r1,2]310x02 0x11 0x42 0x0132 33# CHECK: ldh.x %r2, [%fp,-132]340x7c 0x13 0x42 0xb135 36# CHECK: ld %r0, [%r0,64000]370x30 0x20 0x80 0x0f 0x00 0x00 0x00 0xfa38 39# CHECK: ld %r6, [63920]400x00 0x16 0x06 0x70 0x00 0x00 0xb0 0xf941 42# CHECK: stb %r2, [%sp,35]430x23 0x1c 0x82 0x3044 45# CHECK: st %r7, [63920]460x00 0x1e 0xc0 0x71 0x00 0x00 0xb0 0xf947 48# CHECK: ldb.ab %r1, [%r0,1]490x01 0x10 0x81 0x0450 51# CHECK: stb.ab %r2, [%r0,1]520x01 0x18 0x92 0x0053 54# CHECK: ldh.ab %r3, [%r0,12]550x0C 0x10 0x03 0x0556 57# CHECK: sth.ab %r4, [%r0,18]580x12 0x18 0x14 0x0159 60# CHECK: ld.ab %r5, [%r2,128]610x80 0x12 0x05 0x0462 63# CHECK: st.ab %r6, [%r2,64]640x40 0x1A 0x90 0x0165 66# CHECK: ldb.aw %r7, [%r0,1]670x01 0x10 0x87 0x0268 69# CHECK: stb.aw %r8, [%r0,1]700x01 0x18 0x0A 0x0271 72# CHECK: ldh.aw %r3, [%r0,12]730x0C 0x10 0x03 0x0374 75# CHECK: sth.aw %r3, [%r0,18]760x12 0x18 0xCC 0x0077 78# CHECK: ld.aw %r6, [%r2,128]790x80 0x12 0x06 0x0280 81# CHECK: st.aw %r6, [%r2,64]820x40 0x1A 0x88 0x0183 84# CHECK: ld.aw %r6, [%r2,128]850x80 0x12 0x06 0x0286 87# CHECK: st.aw %r6, [%r2,64]880x40 0x1A 0x88 0x0189 90# CHECK: ldb.x.di.aw %r0, [%r8,8]910x08 0x10 0xC0 0x1A92 93# CHECK: stb.di.ab %r0, [%r9,64]940x40 0x19 0x32 0x1095 96# LR instructions with a U6 immediate bit pattern97# ([33] maps to the [%count0] auxilary register)98 99# CHECK: lr %r0, [33]1000x6a 0x20 0x40 0x08101 102# CHECK: lr %r7, [33]1030x6a 0x27 0x40 0x08104 105# CHECK: lr %r15, [33]1060x6a 0x27 0x40 0x18107 108# CHECK: lr %r22, [33]1090x6a 0x26 0x40 0x28110 111# LR instructions with an S12 immediate bit pattern112 113# CHECK: lr %r0, [33]1140xaa 0x20 0x40 0x08115 116# The following don't necessarily map to real auxilary registers, but117# the different range of numbers helps exercise the S12 decoder.118 119# CHECK: lr %r0, [-33]1200xaa 0x20 0x60 0x08121 122# CHECK: lr %r0, [97]1230xaa 0x20 0x41 0x08124 125# CHECK: lr %r0, [-97]1260xaa 0x20 0x61 0x08127