59 lines · plain
1# RUN: llvm-mc -disassemble -triple armv8 -mattr=+db -show-encoding < %s | FileCheck %s2 3# New v8 ARM instructions4 5# HLT6 70x70 0x00 0x00 0xe18# CHECK: hlt #09 100x7f 0xff 0x0f 0xe111# CHECK: hlt #6553512 130x59 0xf0 0x7f 0xf5140x51 0xf0 0x7f 0xf5150x55 0xf0 0x7f 0xf5160x5d 0xf0 0x7f 0xf517# CHECK: dmb ishld18# CHECK: dmb oshld19# CHECK: dmb nshld20# CHECK: dmb ld21 220x05 0xf0 0x20 0xe323# CHECK: sevl24 25 26# These are the only coprocessor instructions that remain defined in ARMv827# (The operations on p10/p11 disassemble into FP/NEON instructions)28 290x10 0x0e 0x00 0xee30# CHECK: mcr p1431 320x10 0x0f 0x00 0xee33# CHECK: mcr p1534 350x10 0x0e 0x10 0xee36# CHECK: mrc p1437 380x10 0x0f 0x10 0xee39# CHECK: mrc p1540 410x00 0x0e 0x40 0xec42# CHECK: mcrr p1443 440x00 0x0f 0x40 0xec45# CHECK: mcrr p1546 470x00 0x0e 0x50 0xec48# CHECK: mrrc p1449 500x00 0x0f 0x50 0xec51# CHECK: mrrc p1552 530x00 0x0e 0x80 0xec54# CHECK: stc p1455 560x00 0x0e 0x90 0xec57# CHECK: ldc p1458 59