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1# RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple armv7 2>&1 | FileCheck %s2 3# This file is checking ARMv7 encodings which are globally invalid, usually due4# to the constraints of the instructions not being met. For example invalid5# combinations of registers.6 7 8#------------------------------------------------------------------------------9# Undefined encodings for bfi10#------------------------------------------------------------------------------11 12# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4)13# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 014# -------------------------------------------------------------------------------------------------15# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0|16# -------------------------------------------------------------------------------------------------17#18# if d == 15 then UNPREDICTABLE;19[0x16 0xf0 0xcf 0xe7]20# CHECK: potentially undefined instruction encoding21# CHECK-NEXT: [0x16 0xf0 0xcf 0xe7]22 23#------------------------------------------------------------------------------24# Undefined encodings for cdp225#------------------------------------------------------------------------------26 27[0xe0 0x6a 0x0c 0xfe]28# CHECK: invalid instruction encoding29# CHECK-NEXT: [0xe0 0x6a 0x0c 0xfe]30 31 32#------------------------------------------------------------------------------33# Undefined encodings for cps*34#------------------------------------------------------------------------------35 36# invalid imod value (0b01)37[0xc0 0x67 0x4 0xf1]38# CHECK: invalid instruction encoding39# CHECK-NEXT: [0xc0 0x67 0x4 0xf1]40 41# invalid (imod, M, iflags) combination42[0x93 0x00 0x02 0xf1]43# CHECK: potentially undefined instruction encoding44# CHECK-NEXT: [0x93 0x00 0x02 0xf1]45 46# CPS: various encodings that are ambiguous with other instructions47[0x9f 0xff 0x4e 0xf1]48# CHECK: invalid instruction encoding49# CHECK-NEXT: [0x9f 0xff 0x4e 0xf1]50 51[0x80 0x80 0x2c 0xf1]52# CHECK: invalid instruction encoding53# CHECK-NEXT: [0x80 0x80 0x2c 0xf1]54 55[0xce 0x3f 0x28 0xf1]56# CHECK: invalid instruction encoding57# CHECK-NEXT: [0xce 0x3f 0x28 0xf1]58 59[0x80 0x00 0x20 0xf1]60# CHECK: invalid instruction encoding61# CHECK-NEXT: [0x80 0x00 0x20 0xf1]62 63[0xa0 0x00 0x00 0xf1]64# CHECK: invalid instruction encoding65# CHECK-NEXT: [0xa0 0x00 0x00 0xf1]66 67 68#------------------------------------------------------------------------------69# Undefined encoding space for hint instructions70#------------------------------------------------------------------------------71 72[0xfe 0xf0 0x20 0xf3]73# CHECK: invalid instruction encoding74# CHECK-NEXT: [0xfe 0xf0 0x20 0xf3]75 76 77#------------------------------------------------------------------------------78# Undefined encodings for ldc79#------------------------------------------------------------------------------80 81# Opcode=0 Name=PHI Format=(42)82# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 083# -------------------------------------------------------------------------------------------------84# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0|85# -------------------------------------------------------------------------------------------------86#87# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.88 89[0x92 0xb4 0x1f 0xdc]90# CHECK: invalid instruction encoding91# CHECK-NEXT: [0x92 0xb4 0x1f 0xdc]92 93 94#------------------------------------------------------------------------------95# Undefined encodings for ldm96#------------------------------------------------------------------------------97 98# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)99# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0100# -------------------------------------------------------------------------------------------------101# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|102# -------------------------------------------------------------------------------------------------103#104# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction105# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction106 107[0x32 0xb1 0x99 0xf8]108# CHECK: invalid instruction encoding109# CHECK-NEXT: [0x32 0xb1 0x99 0xf8]110 111 112#------------------------------------------------------------------------------113# Undefined encodings for ldr114#------------------------------------------------------------------------------115 116# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)117# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0118# -------------------------------------------------------------------------------------------------119# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|120# -------------------------------------------------------------------------------------------------121#122# if m == 15 then UNPREDICTABLE123 124[0x8f 0x60 0xb7 0xe7]125# CHECK: potentially undefined instruction encoding126# CHECK-NEXT: [0x8f 0x60 0xb7 0xe7]127 128# LDR (register) has encoding Inst{4} = 0.129[0xba 0xae 0x9f 0x57]130# CHECK: invalid instruction encoding131# CHECK-NEXT: [0xba 0xae 0x9f 0x57]132 133# LDR_PRE/POST has encoding Inst{4} = 0.134[0xde 0x69 0x18 0x46]135# CHECK: invalid instruction encoding136# CHECK-NEXT: [0xde 0x69 0x18 0x46]137 138# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)139# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0140# -------------------------------------------------------------------------------------------------141# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1|142# -------------------------------------------------------------------------------------------------143#144# if wback && (n == 15 || n == t) then UNPREDICTABLE145[0x05 0x70 0xd7 0xe6]146# CHECK: potentially undefined instruction encoding147# CHECK-NEXT: [0x05 0x70 0xd7 0xe6]148 149#------------------------------------------------------------------------------150# Undefined encodings for ldrexd151#------------------------------------------------------------------------------152 153# Opcode=242 Name=LDREXD Format=ARM_FORMAT_LDSTEX(6)154# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0155# -------------------------------------------------------------------------------------------------156# | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 1: 1: 1|157# -------------------------------------------------------------------------------------------------158#159 160# ARM v8 Architecture Reference Manual F5.1.84 LDREXD161# t = UInt(Rt); t2 = t + 1; n = UInt(Rn);162# if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;163 164[0x9f 0x1f 0xb3 0xe1]165# CHECK: potentially undefined instruction encoding166# CHECK-NEXT: [0x9f 0x1f 0xb3 0xe1]167 168# FIXME: should be potentially undefined but no register pair R14_R15 defined to169# to return.170[0x9f 0xef 0xb3 0xe1]171# CHECK: invalid instruction encoding172# CHECK-NEXT: [0x9f 0xef 0xb3 0xe1]173 174#------------------------------------------------------------------------------175# Undefined encodings for mcr176#------------------------------------------------------------------------------177 178# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)179# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0180# -------------------------------------------------------------------------------------------------181# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1|182# -------------------------------------------------------------------------------------------------183#184# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C185 186[0x1b 0x1b 0xa0 0x2e]187# CHECK: invalid instruction encoding188# CHECK-NEXT: [0x1b 0x1b 0xa0 0x2e]189 190 191#------------------------------------------------------------------------------192# Undefined encodings for mov/lsl193#------------------------------------------------------------------------------194 195# Opcode=0 Name=PHI Format=(42)196# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0197# -------------------------------------------------------------------------------------------------198# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|199# -------------------------------------------------------------------------------------------------200# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.201# The instruction is UNPREDICTABLE, and is not a valid instruction.202#203# See also204# A8.6.88 LSL (immediate)205# A8.6.98 MOV (shifted register), and206# I.1 Instruction encoding diagrams and pseudocode207 208[0x2 0xd1 0xbc 0xf1]209# CHECK: invalid instruction encoding210# CHECK-NEXT: [0x2 0xd1 0xbc 0xf1]211 212 213# Opcode=0 Name=PHI Format=(42)214# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0215# -------------------------------------------------------------------------------------------------216# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|217# -------------------------------------------------------------------------------------------------218# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.219# The instruction is UNPREDICTABLE, and is not a valid instruction.220#221# See also222# A8.6.97 MOV (register)223 224[0x2 0xd0 0xbc 0xf1]225# CHECK: invalid instruction encoding226# CHECK-NEXT: [0x2 0xd0 0xbc 0xf1]227 228# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)229# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0230# -------------------------------------------------------------------------------------------------231# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|232# -------------------------------------------------------------------------------------------------233# A8.6.89 LSL (register): Inst{7-4} = 0b0001234[0x93 0x42 0xa0 0xd1]235# CHECK: invalid instruction encoding236# CHECK-NEXT: [0x93 0x42 0xa0 0xd1]237 238# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4)239# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0240# -------------------------------------------------------------------------------------------------241# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|242# -------------------------------------------------------------------------------------------------243#244# if d == 15 then UNPREDICTABLE245[0x00 0xf0 0x41 0xe3]246# CHECK: potentially undefined instruction encoding247# CHECK-NEXT: [0x00 0xf0 0x41 0xe3]248 249 250#------------------------------------------------------------------------------251# Undefined encodings for mrrc2252#------------------------------------------------------------------------------253 254[0x00 0x1a 0x50 0xfc]255# CHECK: invalid instruction encoding256# CHECK-NEXT: [0x00 0x1a 0x50 0xfc]257 258 259#------------------------------------------------------------------------------260# Undefined encodings for msr (imm)261#------------------------------------------------------------------------------262 263# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)264# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0265# -------------------------------------------------------------------------------------------------266# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|267# -------------------------------------------------------------------------------------------------268#269# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)270# The hints instructions have more specific encodings, so if mask == 0,271# we should reject this as an invalid instruction.272 273[0xa7 0xf1 0x20 0x3]274# CHECK: invalid instruction encoding275# CHECK-NEXT: [0xa7 0xf1 0x20 0x3]276 277 278#------------------------------------------------------------------------------279# Undefined encodings for sbfx280#------------------------------------------------------------------------------281 282# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4)283# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0284# -------------------------------------------------------------------------------------------------285# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|286# -------------------------------------------------------------------------------------------------287#288# if d == 15 || n == 15 then UNPREDICTABLE;289 290[0x5f 0x54 0xa7 0xe7]291# CHECK: potentially undefined instruction encoding292# CHECK-NEXT: [0x5f 0x54 0xa7 0xe7]293 294#------------------------------------------------------------------------------295# Undefined encodings for smlad296#------------------------------------------------------------------------------297 298# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)299# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0300# -------------------------------------------------------------------------------------------------301# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|302# -------------------------------------------------------------------------------------------------303#304# A8.6.167305# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE306 307[0x1b 0x68 0xf 0x97]308# CHECK: potentially undefined instruction encoding309# CHECK-NEXT: [0x1b 0x68 0xf 0x97]310 311 312#------------------------------------------------------------------------------313# Undefined encodings for srs314#------------------------------------------------------------------------------315 316# Opcode=0 Name=PHI Format=(42)317# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0318# -------------------------------------------------------------------------------------------------319# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|320# -------------------------------------------------------------------------------------------------321# Unknown format322#323# B6.1.10 SRS324# Inst{19-8} = 0xd05325# Inst{7-5} = 0b000326 327[0x83 0x1c 0xc5 0xf8]328# CHECK: invalid instruction encoding329# CHECK-NEXT: [0x83 0x1c 0xc5 0xf8]330 331[0x00 0x00 0x20 0xf8]332# CHECK: invalid instruction encoding333# CHECK-NEXT: [0x00 0x00 0x20 0xf8]334 335[0xff 0xff 0xaf 0xf8]336# CHECK: invalid instruction encoding337# CHECK-NEXT: [0xff 0xff 0xaf 0xf8]338 339[0x13 0x00 0xa0 0xf8]340# CHECK: invalid instruction encoding341# CHECK-NEXT: [0x13 0x00 0xa0 0xf8]342 343#------------------------------------------------------------------------------344# Undefined encodings for sxtb345#------------------------------------------------------------------------------346 347# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)348# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0349# -------------------------------------------------------------------------------------------------350# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|351# -------------------------------------------------------------------------------------------------352#353# A8.6.223 SXTB354# if d == 15 || m == 15 then UNPREDICTABLE;355 356[0x75 0xf4 0xaf 0xe6]357# CHECK: potentially undefined instruction encoding358# CHECK-NEXT: [0x75 0xf4 0xaf 0xe6]359 360#------------------------------------------------------------------------------361# Undefined encodings for NEON umaal362#------------------------------------------------------------------------------363 364# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)365# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0366# -------------------------------------------------------------------------------------------------367# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0|368# -------------------------------------------------------------------------------------------------369#370# A8.6.244 UMAAL371# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;372[0x98 0xbf 0x4f 0xf0]373# CHECK: invalid instruction encoding374# CHECK-NEXT: [0x98 0xbf 0x4f 0xf0]375 376#------------------------------------------------------------------------------377# Undefined encodings for NEON vcvt (float <-> fixed)378#------------------------------------------------------------------------------379 380# imm6=0b0xxxxx -> UNDEFINED381[0x1e 0xcf 0x92 0xf3]382# CHECK: invalid instruction encoding383# CHECK-NEXT: [0x1e 0xcf 0x92 0xf3]384 385[0x3e 0xcf 0x92 0xf3]386# CHECK: invalid instruction encoding387# CHECK-NEXT: [0x3e 0xcf 0x92 0xf3]388 389 390#------------------------------------------------------------------------------391# Undefined encodings for NEON vext392#------------------------------------------------------------------------------393 394# invalid imm4 value (0b1xxx)395# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;396[0x8f 0xf9 0xf7 0xf2]397# CHECK: invalid instruction encoding398# CHECK-NEXT: [0x8f 0xf9 0xf7 0xf2]399 400#------------------------------------------------------------------------------401# Undefined encodings for NEON vldmsdb402#------------------------------------------------------------------------------403 404# core registers out of range405[0xa5 0xba 0x72 0xed]406# CHECK: potentially undefined instruction encoding407# CHECK-NEXT: [0xa5 0xba 0x72 0xed]408 409 410#------------------------------------------------------------------------------411# Undefined encodings for NEON vmov412#------------------------------------------------------------------------------413 414# VMOV cmode=0b1111 op=1 is UNDEFINED415[0x70 0xef 0xc7 0xf3]416# CHECK: invalid instruction encoding417# CHECK-NEXT: [0x70 0xef 0xc7 0xf3]418 419# VMOV cmode=0b1111 op=1 is UNDEFINED420[0x30 0x0f 0x80 0xf3]421# CHECK: invalid instruction encoding422# CHECK-NEXT: [0x30 0x0f 0x80 0xf3]423 424 425#------------------------------------------------------------------------------426# Undefined encodings for NEON vqadd427#------------------------------------------------------------------------------428 429# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)430# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 431# -------------------------------------------------------------------------------------------------432# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|433# -------------------------------------------------------------------------------------------------434#435# Qm -> bit[0] == 0, otherwise UNDEFINED436[0xdb 0xe0 0x40 0xf2]437# CHECK: invalid instruction encoding438# CHECK-NEXT: [0xdb 0xe0 0x40 0xf2]439 440 441#------------------------------------------------------------------------------442# Undefined encodings for NEON vld/vst443#------------------------------------------------------------------------------444 445# A8.6.393 VST2 (multiple 2-element structures)446[0xb3 0x09 0x03 0xf4]447# CHECK: invalid instruction encoding448# CHECK-NEXT: [0xb3 0x09 0x03 0xf4]449 450# size == '11' ==> UNDEFINED451[0xc3 0x08 0x03 0xf4]452# CHECK: invalid instruction encoding453# CHECK-NEXT: [0xc3 0x08 0x03 0xf4]454 455# type == '1000' and align == '11' ==> UNDEFINED456[0xb3 0x08 0x03 0xf4]457# CHECK: invalid instruction encoding458# CHECK-NEXT: [0xb3 0x08 0x03 0xf4]459 460# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined461[0xaf 0xb7 0x07 0xf4]462# CHECK: invalid instruction encoding463# CHECK-NEXT: [0xaf 0xb7 0x07 0xf4]464 465# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined466[0xbf 0xb7 0x07 0xf4]467# CHECK: invalid instruction encoding468# CHECK-NEXT: [0xbf 0xb7 0x07 0xf4]469 470# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined471[0xbf 0x8a 0x03 0xf4]472# CHECK: invalid instruction encoding473# CHECK-NEXT: [0xbf 0x8a 0x03 0xf4]474 475# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined476[0xaf 0xb6 0x07 0xf4]477# CHECK: invalid instruction encoding478# CHECK-NEXT: [0xaf 0xb6 0x07 0xf4]479 480# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined481[0xbf 0xb6 0x07 0xf4]482# CHECK: invalid instruction encoding483# CHECK-NEXT: [0xbf 0xb6 0x07 0xf4]484 485# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined486[0x4f 0xa8 0x07 0xf7]487# CHECK: invalid instruction encoding488# CHECK-NEXT: [0x4f 0xa8 0x07 0xf7]489 490# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined491[0x4f 0xa9 0x07 0xf7]492# CHECK: invalid instruction encoding493# CHECK-NEXT: [0x4f 0xa9 0x07 0xf7]494 495# VST3 multi-element, size = 0b11 -> undefined496[0xbf 0xa4 0x0b 0xf4]497# CHECK: invalid instruction encoding498# CHECK-NEXT: [0xbf 0xa4 0x0b 0xf4]499 500# VST3 multi-element, align = 0b10 -> undefined501[0x6f 0xa4 0x0b 0xf4]502# CHECK: invalid instruction encoding503# CHECK-NEXT: [0x6f 0xa4 0x0b 0xf4]504 505# VST3 multi-element, align = 0b11 -> undefined506[0x7f 0xa4 0x0b 0xf4]507# CHECK: invalid instruction encoding508# CHECK-NEXT: [0x7f 0xa4 0x0b 0xf4]509 510# VST4 multi-element, size = 0b11 -> undefined511[0xcf 0x50 0x03 0xf4]512# CHECK: invalid instruction encoding513# CHECK-NEXT: [0xcf 0x50 0x03 0xf4]514 515 516# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)517# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 518# -------------------------------------------------------------------------------------------------519# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1|520# -------------------------------------------------------------------------------------------------521# 522# 'a' == 1 and data_size == 8 is invalid523[0x3d 0x3c 0xa0 0xf4]524# CHECK: invalid instruction encoding525# CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4]526 527 528#------------------------------------------------------------------------------529# Undefined encodings for MSR/MRS (banked register)530#------------------------------------------------------------------------------531# These have a banked register encoding of 0b111111, which is unallocated.532 533# msr <invalid>, r0534[0x00,0xf3,0x6f,0xe1]535# CHECK: invalid instruction encoding536# CHECK-NEXT: [0x00,0xf3,0x6f,0xe1]537 538# mrs r0, <invalid>539[0x00,0x03,0x4f,0xe1]540# CHECK: invalid instruction encoding541# CHECK-NEXT: [0x00,0x03,0x4f,0xe1]542