433 lines · plain
1# RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V72# RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s3 4# This file is checking Thumbv7 encodings which are globally invalid, usually due5# to the constraints of the instructions not being met. For example invalid6# combinations of registers.7 8#------------------------------------------------------------------------------9# Undefined encoding for b.cc10#------------------------------------------------------------------------------11 12# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)13# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 014# -------------------------------------------------------------------------------------------------15# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|16# -------------------------------------------------------------------------------------------------17#18# A8.6.16 B19# if cond<3:1> == '111' then SEE "Related Encodings"20 21[0xaf 0xf7 0x44 0x8b]22# CHECK: warning: invalid instruction encoding23# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b]24 25#------------------------------------------------------------------------------26# Undefined encoding for it27#------------------------------------------------------------------------------28 29[0xff 0xbf 0x6b 0x80 0x00 0x75]30# CHECK: potentially undefined instruction encoding31# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75]32 33[0x50 0xbf] # hint #5; legal as the third instruction for the iteee above34 35# Two warnings from this block since there are two instructions in there36[0xdb 0xbf 0x42 0xbb]37# CHECK: potentially undefined instruction encoding38# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]39# CHECK: potentially undefined instruction encoding40# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]41 42#------------------------------------------------------------------------------43# Undefined encoding for ldm44#------------------------------------------------------------------------------45 46# Writeback is not allowed is Rn is in the target register list.47[0xb4 0xe8 0x34 0x04]48# CHECK: potentially undefined instruction encoding49# CHECK-NEXT: [0xb4 0xe8 0x34 0x04]50 51 52#------------------------------------------------------------------------------53# Undefined encoding for ldrd54#------------------------------------------------------------------------------55 56# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)57# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 58# -------------------------------------------------------------------------------------------------59# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|60# -------------------------------------------------------------------------------------------------61#62# A8.6.66 LDRD (immediate)63# if Rn = '1111' then SEE LDRD (literal)64# A8.6.67 LDRD (literal)65# Inst{21} = 066 67[0xff 0xe9 0x0 0xeb]68# CHECK: potentially undefined69# CHECK-NEXT: [0xff 0xe9 0x0 0xeb]70 71 72#------------------------------------------------------------------------------73# Undefined encodings for ldrbt74#------------------------------------------------------------------------------75 76# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)77# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 078# -------------------------------------------------------------------------------------------------79# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|80# -------------------------------------------------------------------------------------------------81#82# The unpriviledged Load/Store cannot have SP or PC as Rt.83[0x10 0xf8 0x3 0xfe]84# CHECK: potentially undefined instruction encoding85# CHECK-NEXT: [0x10 0xf8 0x3 0xfe]86 87 88#------------------------------------------------------------------------------89# Undefined encodings for ldrsh90#------------------------------------------------------------------------------91 92# invalid LDRSHs Rt=PC93[0x30 0xf9 0x00 0xf0]94# CHECK: invalid instruction encoding95# CHECK-NEXT: [0x30 0xf9 0x00 0xf0]96 97# invalid LDRSHi8 Rt=PC98[0x30 0xf9 0x00 0xfc]99# CHECK: invalid instruction encoding100# CHECK-NEXT: [0x30 0xf9 0x00 0xfc]101 102# invalid LDRSHi12 Rt=PC103[0xb0 0xf9 0x00 0xf0]104# CHECK: invalid instruction encoding105# CHECK-NEXT: [0xb0 0xf9 0x00 0xf0]106 107# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)108# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0109# -------------------------------------------------------------------------------------------------110# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|111# -------------------------------------------------------------------------------------------------112#113# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"114[0x35 0xf9 0x00 0xfc]115# CHECK: invalid instruction encoding116# CHECK-NEXT: [0x35 0xf9 0x00 0xfc]117 118# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)119# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0120# -------------------------------------------------------------------------------------------------121# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|122# -------------------------------------------------------------------------------------------------123#124# if Rt = '1111' then SEE "Unallocated memory hints"125[0xb3 0xf9 0xdf 0xf8]126# CHECK: invalid instruction encoding127# CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8]128 129 130#------------------------------------------------------------------------------131# Undefined encoding for push132#------------------------------------------------------------------------------133 134# SP and PC are not allowed in the register list on STM instructions in Thumb2.135[0x2d 0xe9 0xf7 0xb6]136# CHECK: invalid instruction encoding137# CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6]138 139 140#------------------------------------------------------------------------------141# Undefined encoding for stmia142#------------------------------------------------------------------------------143 144# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)145# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0146# -------------------------------------------------------------------------------------------------147# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|148# -------------------------------------------------------------------------------------------------149#150# if BitCount(registers) < 1 then UNPREDICTABLE151[0x00 0xc7]152# CHECK: invalid instruction encoding153# CHECK-NEXT: [0x00 0xc7]154 155 156#------------------------------------------------------------------------------157# Undefined encodings for str158#------------------------------------------------------------------------------159 160# invalid STRi12 Rn=PC161[0xcf 0xf8 0x00 0x00]162# CHECK: invalid instruction encoding163# CHECK-NEXT: [0xcf 0xf8 0x00 0x00]164 165# invalid STRi8 Rn=PC166[0x4f 0xf8 0x00 0x0c]167# CHECK: invalid instruction encoding168# CHECK-NEXT: [0x4f 0xf8 0x00 0x0c]169 170# invalid STRs Rn=PC171[0x4f 0xf8 0x00 0x00]172# CHECK: invalid instruction encoding173# CHECK-NEXT: [0x4f 0xf8 0x00 0x00]174 175# invalid STRBi12 Rn=PC176[0x0f 0xf8 0x00 0x00]177# CHECK: invalid instruction encoding178# CHECK-NEXT: [0x0f 0xf8 0x00 0x00]179 180# invalid STRBi8 Rn=PC181[0x0f 0xf8 0x00 0x0c]182# CHECK: invalid instruction encoding183# CHECK-NEXT: [0x0f 0xf8 0x00 0x0c]184 185# invalid STRBs Rn=PC186[0x0f 0xf8 0x00 0x00]187# CHECK: invalid instruction encoding188# CHECK-NEXT: [0x0f 0xf8 0x00 0x00]189 190# invalid STRHi12 Rn=PC191[0xaf 0xf8 0x00 0x00]192# CHECK: invalid instruction encoding193# CHECK-NEXT: [0xaf 0xf8 0x00 0x00]194 195# invalid STRHi8 Rn=PC196[0x2f 0xf8 0x00 0x0c]197# CHECK: invalid instruction encoding198# CHECK-NEXT: [0x2f 0xf8 0x00 0x0c]199 200# invalid STRHs Rn=PC201[0x2f 0xf8 0x00 0x00]202# CHECK: invalid instruction encoding203# CHECK-NEXT: [0x2f 0xf8 0x00 0x00]204 205# invalid STRBT Rn=PC206[0x0f 0xf8 0x00 0x0e]207# CHECK: invalid instruction encoding208# CHECK-NEXT: [0x0f 0xf8 0x00 0x0e]209 210# invalid STRHT Rn=PC211[0x2f 0xf8 0x00 0x0e]212# CHECK: invalid instruction encoding213# CHECK-NEXT: [0x2f 0xf8 0x00 0x0e]214 215# invalid STRT Rn=PC216[0x4f 0xf8 0x00 0x0e]217# CHECK: invalid instruction encoding218# CHECK-NEXT: [0x4f 0xf8 0x00 0x0e]219 220# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)221# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0222# -------------------------------------------------------------------------------------------------223# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|224# -------------------------------------------------------------------------------------------------225#226# if Rn == '1111' then UNDEFINED227 228[0x4f 0xf8 0xff 0xeb]229# CHECK: invalid instruction encoding230# CHECK-NEXT: [0x4f 0xf8 0xff 0xeb]231 232#------------------------------------------------------------------------------233# Undefined encodings for strd234#------------------------------------------------------------------------------235 236# Rt == Rn is UNPREDICTABLE237[0xe4 0xe9 0x02 0x46]238# CHECK: warning: potentially undefined instruction encoding239# CHECK-NEXT: [0xe4 0xe9 0x02 0x46]240 241#------------------------------------------------------------------------------242# Undefined encodings for NEON vld instructions243#------------------------------------------------------------------------------244 245# size = '00' and index_align == '0001' so UNDEFINED246[0xa0 0xf9 0x10 0x08]247# CHECK: invalid instruction encoding248# CHECK-NEXT: [0xa0 0xf9 0x10 0x08]249 250 251# vld3252 253# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30)254# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0255# -------------------------------------------------------------------------------------------------256# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0|257# -------------------------------------------------------------------------------------------------258#259# A8.6.315 VLD3 (single 3-element structure to all lanes)260# The a bit must be encoded as 0.261 262[0xa2 0xf9 0x92 0x2e]263# CHECK: invalid instruction encoding264# CHECK-NEXT: [0xa2 0xf9 0x92 0x2e]265 266 267# Some vld4 ones268# size == '11' and a == '0' so UNDEFINED269[0xa0 0xf9 0xc0 0x0f]270# CHECK: invalid instruction encoding271# CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f]272 273[0xa0 0xf9 0x30 0x0b]274# CHECK: invalid instruction encoding275# CHECK-NEXT: [0xa0 0xf9 0x30 0x0b]276 277 278# VLD1 multi-element, type=0b1010 align=0b11279[0x24 0xf9 0xbf 0x8a]280# CHECK: invalid instruction encoding281# CHECK-NEXT: [0x24 0xf9 0xbf 0x8a]282 283# VLD1 multi-element type=0b0111 align=0b1x284[0x24 0xf9 0xbf 0x87]285# CHECK: invalid instruction encoding286# CHECK-NEXT: [0x24 0xf9 0xbf 0x87]287 288# VLD1 multi-element type=0b0010 align=0b1x289[0x24 0xf9 0xbf 0x86]290# CHECK: invalid instruction encoding291# CHECK-NEXT: [0x24 0xf9 0xbf 0x86]292 293# VLD2 multi-element size=0b11294[0x60 0xf9 0xcf 0x08]295# CHECK: invalid instruction encoding296# CHECK-NEXT: [0x60 0xf9 0xcf 0x08]297 298# VLD2 multi-element type=0b1111 align=0b11299[0x60 0xf9 0xbf 0x08]300# CHECK: invalid instruction encoding301# CHECK-NEXT: [0x60 0xf9 0xbf 0x08]302 303# VLD2 multi-element type=0b1001 align=0b11304[0x60 0xf9 0xbf 0x09]305# CHECK: invalid instruction encoding306# CHECK-NEXT: [0x60 0xf9 0xbf 0x09]307 308# VLD3 multi-element size=0b11309[0x60 0xf9 0x7f 0x04]310# CHECK: invalid instruction encoding311# CHECK-NEXT: [0x60 0xf9 0x7f 0x04]312 313# VLD3 multi-element align=0b1x314[0x60 0xf9 0xcf 0x04]315# CHECK: invalid instruction encoding316# CHECK-NEXT: [0x60 0xf9 0xcf 0x04]317 318# VLD4 multi-element size=0b11319[0x60 0xf9 0xcd 0x11]320# CHECK: invalid instruction encoding321# CHECK-NEXT: [0x60 0xf9 0xcd 0x11]322 323 324#------------------------------------------------------------------------------325# Undefined encodings for NEON vst1326#------------------------------------------------------------------------------327 328# size == '10' and index_align == '0001' so UNDEFINED329[0x80 0xf9 0x10 0x08]330# CHECK: invalid instruction encoding331# CHECK-NEXT: [0x80 0xf9 0x10 0x08]332 333# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)334# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0335# -------------------------------------------------------------------------------------------------336# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|337# -------------------------------------------------------------------------------------------------338#339# A8.6.391 VST1 (multiple single elements)340# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]341# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>342# contains two or four registers. rdar://11220250343[0x00 0xf9 0x2f 0x06]344# CHECK: invalid instruction encoding345# CHECK-NEXT: [0x00 0xf9 0x2f 0x06]346 347#------------------------------------------------------------------------------348# Undefined encodings for NEON vst4349#------------------------------------------------------------------------------350 351[0x80 0xf9 0x30 0x0b]352# CHECK: invalid instruction encoding353# CHECK-NEXT: [0x80 0xf9 0x30 0x0b]354 355 356#------------------------------------------------------------------------------357# Unpredictable STMs358#------------------------------------------------------------------------------359 360# 32-bit Thumb STM instructions cannot have a writeback register which appears361# in the list.362 363[0xa1 0xe8 0x07 0x04]364# CHECK: warning: potentially undefined instruction encoding365# CHECK-NEXT: [0xa1 0xe8 0x07 0x04]366 367[0x21 0xe9 0x07 0x04]368# CHECK: warning: potentially undefined instruction encoding369# CHECK-NEXT: [0x21 0xe9 0x07 0x04]370 371#------------------------------------------------------------------------------372# SP is invalid as rGPR before ARMv8373#------------------------------------------------------------------------------374 375[0x00 0xf0 0x00 0x0d]376# CHECK-V7: warning: potentially undefined instruction encoding377# CHECK-V7-NEXT: [0x00 0xf0 0x00 0x0d]378 379[0x63 0xeb 0x2d 0x46]380# CHECK-V7: warning: potentially undefined instruction encoding381# CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46]382 383#------------------------------------------------------------------------------384# Undefined encodings for MSR/MRS (banked register)385#------------------------------------------------------------------------------386# These have a banked register encoding of 0b111111, which is unallocated.387 388# msr <invalid>, r0389[0x90,0xf3,0x30,0x8f]390# CHECK: invalid instruction encoding391# CHECK-NEXT: [0x90,0xf3,0x30,0x8f]392 393# mrs r0, <invalid>394[0xff,0xf3,0x30,0x80]395# CHECK: invalid instruction encoding396# CHECK-NEXT: [0xff,0xf3,0x30,0x80]397 398#------------------------------------------------------------------------------399# If dest is sp then source must be in T2 add/sub400#------------------------------------------------------------------------------401 402[0x05,0xf1,0x01,0x0d]403[0x07,0xf2,0x04,0x0d]404[0x03,0xeb,0x02,0x0d]405[0x03,0xeb,0xc5,0x0d]406# CHECK-V7: warning: potentially undefined instruction encoding407# CHECK-V7-NEXT: [0x05,0xf1,0x01,0x0d]408# CHECK-V7: warning: potentially undefined instruction encoding409# CHECK-V7-NEXT: [0x07,0xf2,0x04,0x0d]410# CHECK-V7: warning: potentially undefined instruction encoding411# CHECK-V7-NEXT: [0x03,0xeb,0x02,0x0d]412# CHECK-V7: warning: potentially undefined instruction encoding413# CHECK-V7-NEXT: [0x03,0xeb,0xc5,0x0d]414 415 416[0xa5,0xf1,0x01,0x0d]417[0xa7,0xf2,0x04,0x0d]418[0xa3,0xeb,0x02,0x0d]419[0xa3,0xeb,0xc5,0x0d]420# CHECK-V7: warning: potentially undefined instruction encoding421# CHECK-V7-NEXT: [0xa5,0xf1,0x01,0x0d]422# CHECK-V7: warning: potentially undefined instruction encoding423# CHECK-V7-NEXT: [0xa7,0xf2,0x04,0x0d]424# CHECK-V7: warning: potentially undefined instruction encoding425# CHECK-V7-NEXT: [0xa3,0xeb,0x02,0x0d]426# CHECK-V7: warning: potentially undefined instruction encoding427# CHECK-V7-NEXT: [0xa3,0xeb,0xc5,0x0d]428# CHECK-V7-NEXT: ^429[0x0f,0xf2,0x00,0x4d]430# CHECK-V7-NEXT: warning: potentially undefined instruction encoding431# CHECK-V7-NEXT: [0x0f,0xf2,0x00,0x4d]432# CHECK-V7-NEXT: ^433