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1# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding %s 2> %t | FileCheck %s2# RUN: FileCheck --check-prefix=WARN < %t %s3# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding %s 2> %t | FileCheck %s4# RUN: FileCheck --check-prefix=WARN < %t %s5 6[0x9f 0xec 0x04 0x0a]7# CHECK: vscclrm {s0, s1, s2, s3, vpr}8 9[0xdf,0xec,0x06,0x1a]10# CHECK: vscclrm {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]11 12[0x9f 0xec 0x0c 0x9a]13# CHECK: vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}14 15[0xdf 0xec 0x01 0xfa]16# CHECK: vscclrm {s31, vpr}17 18[0x9f,0xec,0x04,0x0b]19# CHECK: vscclrm {d0, d1, vpr} @ encoding: [0x9f,0xec,0x04,0x0b]20 21[0x9f,0xec,0x08,0x0b]22# CHECK: vscclrm {d0, d1, d2, d3, vpr} @ encoding: [0x9f,0xec,0x08,0x0b]23 24[0x9f,0xec,0x06,0x5b]25# CHECK: vscclrm {d5, d6, d7, vpr} @ encoding: [0x9f,0xec,0x06,0x5b]26 27[0x88 0xbf]28# CHECK: it hi29 30[0xdf 0xec 0x1d 0x1a]31# CHECK: vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}32 33[0xdf,0xec,0x03,0xfa]34# CHECK: vscclrm {s31, d16, vpr} @ encoding: [0xdf,0xec,0x03,0xfa]35 36[0x9f,0xec,0x40,0x0a]37# CHECK: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0a]38 39# If the list size is zero then we get a list of only vpr, and the Vd register40# doesn't matter.41 42[0x9f,0xec,0x00,0x0b]43# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0b]44 45[0xdf,0xec,0x00,0xfb]46# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0b]47 48[0x9f,0xec,0x00,0x0a]49# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0a]50 51[0xdf,0xec,0x00,0xfa]52# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0a]53 54# In double-precision if Vd+size goes past 31 the excess registers are ignored55# and we get a warning.56 57[0x9f,0xec,0xfe,0x0b]58# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding59# CHECK: vscclrm {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0b]60 61[0xdf,0xec,0x04,0xfb]62# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding63# CHECK: vscclrm {d31, vpr} @ encoding: [0xdf,0xec,0x02,0xfb]64 65# In single-precision if Vd+size goes past 63, or if the encoding suggests half66# a d registers, then the excess registers are ignored and we get a warning.67 68[0x9f,0xec,0xff,0x0a]69# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding70# CHECK: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0a]71 72[0xdf,0xec,0x02,0xfa]73# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding74# CHECK: vscclrm {s31, vpr} @ encoding: [0xdf,0xec,0x01,0xfa]75 76[0xdf,0xec,0x23,0xfa]77# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding78vscclrm {s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0xdf,0xec,0x21,0xfa]79