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1# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 52# RUN: llvm-mc -triple=xtensa -mattr=+dfpaccel -disassemble %s | FileCheck -check-prefixes=CHECK-DFPACCEL %s3# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s4 5## Verify that binary code is correctly disassembled with6## DFPACCEL option enabled. Also verify that dissasembling without7## DFPACCEL option generates warnings.8 9[0xa0,0x3e,0xe3]10# CHECK-DFPACCEL: rur a3, f64r_lo11# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding12 13[0xb0,0x3e,0xe3]14# CHECK-DFPACCEL: rur a3, f64r_hi15# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding16 17[0xc0,0x3e,0xe3]18# CHECK-DFPACCEL: rur a3, f64s19# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding20