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1# RUN: llvm-mc -triple=xtensa -mattr=+interrupt -disassemble %s | FileCheck -check-prefixes=CHECK-EXCEPTION %s2# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s3 4## Verify that binary code is correctly disassembled with5## Xtensa interrupt option enabled. Also verify that dissasembling without6## Xtensa interrupt option generates warnings.7 8[0x20,0x61,0x00]9# CHECK-EXCEPTION: rsil a2, 110# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding11 12[0x00,0x71,0x00]13# CHECK-EXCEPTION: waiti 114# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding15 16[0x20, 0xe4, 0x61]17#CHECK-INST: xsr a2, intenable18#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding19 20[0x20, 0xe2, 0x03]21#CHECK-INST: rsr a2, interrupt22#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding23 24[0x20, 0xe3, 0x13]25#CHECK-INST: wsr a2, intclear26#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding27