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1# RUN: llvm-mc -triple=xtensa -mattr=+miscsr -disassemble %s | FileCheck -check-prefixes=CHECK-MISCSR %s2# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s3 4## Verify that binary code is correctly disassembled with5## miscr option enabled. Also verify that dissasembling without6## miscr option generates warnings.7 8[0x30,0xf4,0x61]9# CHECK-MISCSR: xsr a3, misc010# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding11 12[0x30,0xf5,0x61]13# CHECK-MISCSR: xsr a3, misc114# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding15 16[0x30,0xf6,0x61]17# CHECK-MISCSR: xsr a3, misc218# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding19 20[0x30,0xf7,0x61]21# CHECK-MISCSR: xsr a3, misc322# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding23