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1# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V622# RUN: not llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=asm %s 2>%t; FileCheck -check-prefix=CHECK-NOV62 %s < %t3#4 5# Assure that v62 added registers are understood6 7r0=framelimit8r0=framekey9r1:0=c17:1610 11# CHECK-V62: 6a10c000 { r0 = framelimit }12# CHECK-V62: 6a11c000 { r0 = framekey }13# CHECK-V62: 6810c000 { r1:0 = c17:16 }14# CHECK-NOV62: rror: invalid operand for instruction15# CHECK-NOV62: rror: invalid operand for instruction16# CHECK-NOV62: rror: invalid operand for instruction17 18r0=pktcountlo19r0=pktcounthi20r1:0=c19:1821r1:0=pktcount22 23# CHECK-V62: 6a12c000 { r0 = pktcountlo }24# CHECK-V62: 6a13c000 { r0 = pktcounthi }25# CHECK-V62: 6812c000 { r1:0 = c19:18 }26# CHECK-V62: 6812c000 { r1:0 = c19:18 }27# CHECK-NOV62: rror: invalid operand for instruction28# CHECK-NOV62: rror: invalid operand for instruction29# CHECK-NOV62: rror: invalid operand for instruction30# CHECK-NOV62: rror: invalid operand for instruction31 32r0=utimerlo33r0=utimerhi34r1:0=c31:3035r1:0=UTIMER36 37# CHECK-V62: 6a1ec000 { r0 = utimerlo }38# CHECK-V62: 6a1fc000 { r0 = utimerhi }39# CHECK-V62: 681ec000 { r1:0 = c31:30 }40# CHECK-V62: 681ec000 { r1:0 = c31:30 }41# CHECK-NOV62: rror: invalid operand for instruction42# CHECK-NOV62: rror: invalid operand for instruction43# CHECK-NOV62: rror: invalid operand for instruction44# CHECK-NOV62: rror: invalid operand for instruction45