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1# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=+micromips,+eva 2>%t12# RUN: FileCheck %s < %t13 4 addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 45 addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 46 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction8 addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate11 addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate13 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate14 beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction15 beqzc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address16 beqzc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range17 bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction18 bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address19 bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range20 break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate21 break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate22 break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate23 break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate24 break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate25 break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate26 break 1023, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate27 cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate28 cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate29 # FIXME: Check '0 < pos + size <= 32' constraint on ext30 ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate31 ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate32 ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 3233 ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 3234 ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate35 ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate36 ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number37 swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid register number38 swe $5, 8($34) # CHECK: :[[@LINE]]:13: error: invalid register number39 swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset40 lapc $7, 1048576 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 441 lapc $6, -1048580 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 442 lapc $3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 443 lapc $3, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 444 lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction45 lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range46 lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range47 lbu16 $16, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction48 lhu16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction49 lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range50 lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range51 lhu16 $16, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction52 li16 $4, -2 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 12653 li16 $4, 127 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 12654 lsa $4, $2, $3, 0 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 455 lsa $4, $2, $3, 5 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 456 lw16 $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction57 lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range58 lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range59 lw16 $17, 8($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction60 pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate61 pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate62 teq $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number63 teq $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number64 tge $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number65 tge $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number66 tgeu $34, $9, 5 # CHECK: :[[@LINE]]:8: error: invalid register number67 tgeu $8, $35, 6 # CHECK: :[[@LINE]]:12: error: invalid register number68 tlt $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number69 tlt $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number70 tltu $34, $9, 5 # CHECK: :[[@LINE]]:8: error: invalid register number71 tltu $8, $35, 6 # CHECK: :[[@LINE]]:12: error: invalid register number72 tne $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number73 tne $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number74 wait -1 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate75 wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate76 wrpgpr $34, $4 # CHECK: :[[@LINE]]:10: error: invalid register number77 wrpgpr $3, $33 # CHECK: :[[@LINE]]:14: error: invalid register number78 wsbh $34, $4 # CHECK: :[[@LINE]]:8: error: invalid register number79 wsbh $3, $33 # CHECK: :[[@LINE]]:12: error: invalid register number80 jrcaddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 481 jrcaddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 482 jrcaddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 483 jrcaddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 484 jrcaddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 485 jrcaddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 486 jrcaddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 487 jrcaddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 488 jrcaddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 489 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected90 lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected91 lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand92 lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction93 lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction94 lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction95 lwm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction96 lwm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction97 sb16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction98 sb16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range99 sb16 $16, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction100 sb16 $7, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction101 sh16 $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction102 sh16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range103 sh16 $16, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction104 sh16 $7, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction105 sync -1 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate106 sync 32 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate107 sw16 $9, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction108 sw16 $4, 64($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range109 sw16 $16, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction110 sw16 $7, 4($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction111 swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected112 swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected113 swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand114 swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction115 swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction116 swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction117 swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction118 swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction119 mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate120 mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate121 mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate122 mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate123 mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate124 mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate125 mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate126 mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate127 tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction128 tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction129 tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction130 tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction131 tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction132 tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction133 tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction134 tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction135 tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction136 tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction137 tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction138 tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction139 dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction140 dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction141 evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction142 evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction143 jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different144 jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different145 sll $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate146 sll $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate147 sra $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate148 sra $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate149 srl $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate150 srl $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate151 sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate152 sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate153 sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate154 sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate155 srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate156 srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate157 ll $33, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number158 ll $4, 8($33) # CHECK: :[[@LINE]]:12: error: invalid register number159 ll $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled160 ll $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled161 lle $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number162 lle $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number163 lle $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset164 lle $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset165 lwe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number166 lwe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number167 lwe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset168 lwe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset169 sbe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number170 sbe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number171 sbe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset172 sbe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset173 sc $33, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number174 sc $4, 8($33) # CHECK: :[[@LINE]]:12: error: invalid register number175 sc $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled176 sc $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled177 sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number178 sce $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number179 sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset180 sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset181 she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number182 she $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number183 she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset184 she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset185 swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset186 lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number187 lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number188 lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number189 lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number190 lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number191 lhe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number192 lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number193 lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number194 lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset195 lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset196 lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset197 lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset198 lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset199 lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset200 lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset201 lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset202 lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected203 lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected204 lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand205 lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand206 movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction207 movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction208 movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction209 movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction210 rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate211 rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate212 rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate213 rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate214 rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction215 swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected216 swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected217 swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand218 lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction219 # FIXME: This ought to point at the $34 but memory is treated as one operand.220 lwp $16, 8($34) # CHECK: :[[@LINE]]:14: error: invalid register number221 lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset222 lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different223 swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction224 swp $16, 8($34) # CHECK: :[[@LINE]]:14: error: invalid register number225 swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset226 # bposge32 is microMIPS DSP instruction227 bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled228 bc1eqzc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction229 bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address230 bc1eqzc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range231 bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address232 bc1eqzc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range233 bc1nezc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction234 bc1nezc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address235 bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range236 bc1nezc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address237 bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range238 bc2eqzc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid register number239 bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address240 bc2eqzc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range241 bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address242 bc2eqzc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range243 bc2nezc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid register number244 bc2nezc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address245 bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range246 bc2nezc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address247 bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range248 jalrc $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different249 jalrc $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different250 andi $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate251 andi $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate252 andi $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate253 andi $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate254 ori $3, $4, -1 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate255 ori $3, $4, 65536 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate256 ori $3, -1 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate257 ori $3, 65536 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate258 xori $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate259 xori $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate260 xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate261 xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate262 not $3, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction263 lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number264 lb $4, -2147483649($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset265 lb $4, 2147483648($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset266 lb $4, 8($32) # CHECK: :[[@LINE]]:12: error: invalid register number267 lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number268 lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset269 lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset270 lbu $4, 8($32) # CHECK: :[[@LINE]]:13: error: invalid register number271 ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction272 ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset273 ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset274 ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:17: error: invalid register number275 sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction276 sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset277 sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset278 sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:16: error: invalid register number279 lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction280 lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset281 lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset282 lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:16: error: invalid register number283 swc1 $f32, 369($13) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction284 swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset285 swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset286 swc1 $f6, 369($32) # CHECK: :[[@LINE]]:17: error: invalid register number287 ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:8: error: invalid register number288 sdc2 $32, 8($16) # CHECK: :[[@LINE]]:8: error: invalid register number289 lwc2 $32, 16($4) # CHECK: :[[@LINE]]:8: error: invalid register number290 swc2 $32, 777($17) # CHECK: :[[@LINE]]:8: error: invalid register number291 sdc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled292 sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled293 swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled294 swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled295 bgec $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction296 bgec $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different297 bgec $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range298 bgec $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address299 bgec $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range300 bgec $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address301 bltc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction302 bltc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different303 bltc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range304 bltc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address305 bltc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range306 bltc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address307 bgeuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction308 bgeuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different309 bgeuc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range310 bgeuc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address311 bgeuc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range312 bgeuc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address313 bltuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction314 bltuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different315 bltuc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range316 bltuc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address317 bltuc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range318 bltuc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address319 beqc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction320 beqc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different321 beqc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range322 beqc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address323 beqc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range324 beqc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address325 bnec $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction326 bnec $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different327 bnec $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range328 bnec $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address329 bnec $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range330 bnec $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address331 blezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction332 blezc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range333 blezc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address334 blezc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range335 blezc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address336 bgezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction337 bgezc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range338 bgezc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address339 bgezc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range340 bgezc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address341 bgtzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction342 bgtzc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range343 bgtzc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address344 bgtzc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range345 bgtzc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address346 bltzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction347 bltzc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range348 bltzc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address349 bltzc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range350 bltzc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address351 beqzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction352 beqzc $2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range353 beqzc $2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address354 beqzc $2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range355 beqzc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address356 bnezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction357 bnezc $2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range358 bnezc $2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address359 bnezc $2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range360 bnezc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address361 teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate362 teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate363 tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate364 tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate365 tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate366 tgeu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate367 tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate368 tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate369 tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate370 tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate371 tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate372 tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate373 teqi $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled374 tgei $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled375 tgeiu $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled376 tlti $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled377 tltiu $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled378 tnei $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled379 syscall -1 # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate380 syscall $4 # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate381 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:17: error: invalid register number382 lwc2 $1, 16($32) # CHECK: :[[@LINE]]:15: error: invalid register number383 sdc2 $1, 8($32) # CHECK: :[[@LINE]]:14: error: invalid register number384 swc2 $1, 777($32) # CHECK: :[[@LINE]]:16: error: invalid register number385 movn $3, $3, $4 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled386 movz $3, $3, $4 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled387 movt $4, $5, $fcc0 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled388 movf $4, $5, $fcc0 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled389 madd $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled390 maddu $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled391 msub $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled392 msubu $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled393