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1# Instructions that are available for the current ISA but should be rejected by2# the assembler (e.g. invalid set of operands or operand's restrictions not met).3 4# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t15# RUN: FileCheck %s < %t16 7 .text8local_label:9 .set noreorder10 .set noat11 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate12 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate13 aui $4, $4, 65536 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate14 aui $4, $4, -1 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate15 jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different16 jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different17 swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled18 break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate19 break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate20 break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate21 break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate22 break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate23 break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate24 break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate25 lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number26 lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number27 lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number28 lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number29 lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number30 lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number31 lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number32 lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number33 lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset34 lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset35 lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction36 lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction37 lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset38 lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset39 lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction40 lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction41 // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved42 bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled43 bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled44 blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled45 bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled46 bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled47 bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled48 bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled49 bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled50 bgec $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction51 bltc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction52 bgeuc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction53 bltuc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction54 beqc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction55 bnec $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction56 bgec $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different57 bltc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different58 bgeuc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different59 bltuc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different60 beqc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different61 bnec $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different62 blezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction63 bgezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction64 bgtzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction65 bltzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction66 beqzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction67 bnezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction68 bgec $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range69 bgec $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address70 bgec $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range71 bgec $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address72 bltc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range73 bltc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address74 bltc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range75 bltc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address76 bgeuc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range77 bgeuc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address78 bgeuc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range79 bgeuc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address80 bltuc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range81 bltuc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address82 bltuc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range83 bltuc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address84 beqc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range85 beqc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address86 beqc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range87 beqc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address88 bnec $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range89 bnec $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address90 bnec $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range91 bnec $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address92 blezc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range93 blezc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address94 blezc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range95 blezc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address96 bgezc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range97 bgezc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address98 bgezc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range99 bgezc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address100 bgtzc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range101 bgtzc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address102 bgtzc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range103 bgtzc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address104 bltzc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range105 bltzc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address106 bltzc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range107 bltzc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address108 beqzc $2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range109 beqzc $2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address110 beqzc $2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range111 beqzc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address112 bnezc $2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range113 bnezc $2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address114 bnezc $2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range115 bnezc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address116 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate117 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate118 dvp $17, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction119 dvp $17, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction120 dvp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction121 evp $16, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction122 evp $16, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction123 evp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction124 jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different125 jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different126 lapc $7, 1048576 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4127 lapc $6, -1048580 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4128 lapc $3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4129 lapc $3, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4130 ldc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled131 ldc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled132 lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4133 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4134 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate135 pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate136 mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate137 mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate138 mtc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate139 mtc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate140 mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate141 mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate142 mfc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate143 mfc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate144 sdc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled145 sdc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled146 sync -1 # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate147 sync 32 # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate148 lb $32, 8($5) # CHECK: :[[@LINE]]:12: error: invalid register number149 lb $4, -2147483649($5) # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset150 lb $4, 2147483648($5) # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset151 lb $4, 8($32) # CHECK: :[[@LINE]]:18: error: invalid register number152 lbu $32, 8($5) # CHECK: :[[@LINE]]:13: error: invalid register number153 lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset154 lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset155 lbu $4, 8($32) # CHECK: :[[@LINE]]:19: error: invalid register number156 ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction157 ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset158 ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset159 ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:23: error: invalid register number160 sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction161 sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset162 sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset163 sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:22: error: invalid register number164 lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction165 lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset166 lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset167 lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:22: error: invalid register number168 swc1 $f32, 369($13) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction169 swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset170 swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset171 swc1 $f6, 369($32) # CHECK: :[[@LINE]]:23: error: invalid register number172 ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid register number173 ldc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled174 ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled175 sdc2 $32, 8($16) # CHECK: :[[@LINE]]:14: error: invalid register number176 sdc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled177 sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled178 lwc2 $32, 16($4) # CHECK: :[[@LINE]]:14: error: invalid register number179 lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled180 lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled181 swc2 $32, 777($17) # CHECK: :[[@LINE]]:14: error: invalid register number182 swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled183 swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled184