388 lines · plain
1# RUN: llvm-mc -triple=riscv32 --mattr=+xcvalu -M no-aliases -show-encoding %s \2# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR3# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvalu < %s \4# RUN: | llvm-objdump --mattr=+xcvalu --no-print-imm-hex -M no-aliases -d -r - \5# RUN: | FileCheck --check-prefix=CHECK-INSTR %s6# RUN: not llvm-mc -triple riscv32 %s 2>&1 \7# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s8 9cv.addurnr t0, t1, t210# CHECK-INSTR: cv.addurnr t0, t1, t211# CHECK-ENCODING: [0xab,0x32,0x73,0x86]12# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}13 14cv.addurnr a0, a1, a215# CHECK-INSTR: cv.addurnr a0, a1, a216# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x86]17# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}18 19cv.maxu t0, t1, t220# CHECK-INSTR: cv.maxu t0, t1, t221# CHECK-ENCODING: [0xab,0x32,0x73,0x5c]22# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}23 24cv.maxu a0, a1, a225# CHECK-INSTR: cv.maxu a0, a1, a226# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x5c]27# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}28 29cv.subrnr t0, t1, t230# CHECK-INSTR: cv.subrnr t0, t1, t231# CHECK-ENCODING: [0xab,0x32,0x73,0x8c]32# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}33 34cv.subrnr a0, a1, a235# CHECK-INSTR: cv.subrnr a0, a1, a236# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8c]37# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}38 39cv.sle t0, t1, t240# CHECK-INSTR: cv.sle t0, t1, t241# CHECK-ENCODING: [0xab,0x32,0x73,0x52]42# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}43 44cv.slet t0, t1, t245# CHECK-INSTR: cv.sle t0, t1, t246# CHECK-ENCODING: [0xab,0x32,0x73,0x52]47# CHECK-NO-EXT: unrecognized instruction mnemonic48 49cv.sle a0, a1, a250# CHECK-INSTR: cv.sle a0, a1, a251# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x52]52# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}53 54cv.slet a0, a1, a255# CHECK-INSTR: cv.sle a0, a1, a256# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x52]57# CHECK-NO-EXT: unrecognized instruction mnemonic58 59cv.subrn t0, t1, t2, 060# CHECK-INSTR: cv.subrn t0, t1, t2, 061# CHECK-ENCODING: [0xdb,0x32,0x73,0x80]62# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}63 64cv.subrn t0, t1, t2, 1665# CHECK-INSTR: cv.subrn t0, t1, t2, 1666# CHECK-ENCODING: [0xdb,0x32,0x73,0xa0]67# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}68 69cv.subrn a0, a1, zero, 3170# CHECK-INSTR: cv.subrn a0, a1, zero, 3171# CHECK-ENCODING: [0x5b,0xb5,0x05,0xbe]72# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}73 74cv.subnr t0, t1, t275# CHECK-INSTR: cv.subnr t0, t1, t276# CHECK-ENCODING: [0xab,0x32,0x73,0x88]77# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}78 79cv.subnr a0, a1, a280# CHECK-INSTR: cv.subnr a0, a1, a281# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x88]82# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}83 84cv.addunr t0, t1, t285# CHECK-INSTR: cv.addunr t0, t1, t286# CHECK-ENCODING: [0xab,0x32,0x73,0x82]87# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}88 89cv.addunr a0, a1, a290# CHECK-INSTR: cv.addunr a0, a1, a291# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x82]92# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}93 94cv.addurn t0, t1, t2, 095# CHECK-INSTR: cv.addurn t0, t1, t2, 096# CHECK-ENCODING: [0xdb,0x22,0x73,0xc0]97# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}98 99cv.addurn t0, t1, t2, 16100# CHECK-INSTR: cv.addurn t0, t1, t2, 16101# CHECK-ENCODING: [0xdb,0x22,0x73,0xe0]102# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}103 104cv.addurn a0, a1, zero, 31105# CHECK-INSTR: cv.addurn a0, a1, zero, 31106# CHECK-ENCODING: [0x5b,0xa5,0x05,0xfe]107# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}108 109cv.addun t0, t1, t2, 0110# CHECK-INSTR: cv.addun t0, t1, t2, 0111# CHECK-ENCODING: [0xdb,0x22,0x73,0x40]112# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}113 114cv.addun t0, t1, t2, 16115# CHECK-INSTR: cv.addun t0, t1, t2, 16116# CHECK-ENCODING: [0xdb,0x22,0x73,0x60]117# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}118 119cv.addun a0, a1, zero, 31120# CHECK-INSTR: cv.addun a0, a1, zero, 31121# CHECK-ENCODING: [0x5b,0xa5,0x05,0x7e]122# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}123 124cv.clipu t0, t1, 0125# CHECK-INSTR: cv.clipu t0, t1, 0126# CHECK-ENCODING: [0xab,0x32,0x03,0x72]127# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}128 129cv.clipu t0, t1, 16130# CHECK-INSTR: cv.clipu t0, t1, 16131# CHECK-ENCODING: [0xab,0x32,0x03,0x73]132# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}133 134cv.clipu a0, zero, 31135# CHECK-INSTR: cv.clipu a0, zero, 31136# CHECK-ENCODING: [0x2b,0x35,0xf0,0x73]137# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}138 139cv.clip t0, t1, 0140# CHECK-INSTR: cv.clip t0, t1, 0141# CHECK-ENCODING: [0xab,0x32,0x03,0x70]142# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}143 144cv.clip t0, t1, 16145# CHECK-INSTR: cv.clip t0, t1, 16146# CHECK-ENCODING: [0xab,0x32,0x03,0x71]147# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}148 149cv.clip a0, zero, 31150# CHECK-INSTR: cv.clip a0, zero, 31151# CHECK-ENCODING: [0x2b,0x35,0xf0,0x71]152# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}153 154cv.exthz t0, t1155# CHECK-INSTR: cv.exthz t0, t1156# CHECK-ENCODING: [0xab,0x32,0x03,0x62]157# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}158 159cv.exthz a0, a1160# CHECK-INSTR: cv.exthz a0, a1161# CHECK-ENCODING: [0x2b,0xb5,0x05,0x62]162# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}163 164cv.max t0, t1, t2165# CHECK-INSTR: cv.max t0, t1, t2166# CHECK-ENCODING: [0xab,0x32,0x73,0x5a]167# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}168 169cv.max a0, a1, a2170# CHECK-INSTR: cv.max a0, a1, a2171# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x5a]172# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}173 174cv.clipr t0, t1, t2175# CHECK-INSTR: cv.clipr t0, t1, t2176# CHECK-ENCODING: [0xab,0x32,0x73,0x74]177# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}178 179cv.clipr a0, a1, a2180# CHECK-INSTR: cv.clipr a0, a1, a2181# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x74]182# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}183 184cv.subn t0, t1, t2, 0185# CHECK-INSTR: cv.subn t0, t1, t2, 0186# CHECK-ENCODING: [0xdb,0x32,0x73,0x00]187# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}188 189cv.subn t0, t1, t2, 16190# CHECK-INSTR: cv.subn t0, t1, t2, 16191# CHECK-ENCODING: [0xdb,0x32,0x73,0x20]192# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}193 194cv.subn a0, a1, zero, 31195# CHECK-INSTR: cv.subn a0, a1, zero, 31196# CHECK-ENCODING: [0x5b,0xb5,0x05,0x3e]197# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}198 199cv.extbz t0, t1200# CHECK-INSTR: cv.extbz t0, t1201# CHECK-ENCODING: [0xab,0x32,0x03,0x66]202# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}203 204cv.extbz a0, a1205# CHECK-INSTR: cv.extbz a0, a1206# CHECK-ENCODING: [0x2b,0xb5,0x05,0x66]207# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}208 209cv.abs t0, t1210# CHECK-INSTR: cv.abs t0, t1211# CHECK-ENCODING: [0xab,0x32,0x03,0x50]212# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}213 214cv.abs a0, a1215# CHECK-INSTR: cv.abs a0, a1216# CHECK-ENCODING: [0x2b,0xb5,0x05,0x50]217# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}218 219cv.clipur t0, t1, t2220# CHECK-INSTR: cv.clipur t0, t1, t2221# CHECK-ENCODING: [0xab,0x32,0x73,0x76]222# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}223 224cv.clipur a0, a1, a2225# CHECK-INSTR: cv.clipur a0, a1, a2226# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x76]227# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}228 229cv.minu t0, t1, t2230# CHECK-INSTR: cv.minu t0, t1, t2231# CHECK-ENCODING: [0xab,0x32,0x73,0x58]232# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}233 234cv.minu a0, a1, a2235# CHECK-INSTR: cv.minu a0, a1, a2236# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x58]237# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}238 239cv.addn t0, t1, t2, 0240# CHECK-INSTR: cv.addn t0, t1, t2, 0241# CHECK-ENCODING: [0xdb,0x22,0x73,0x00]242# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}243 244cv.addn t0, t1, t2, 16245# CHECK-INSTR: cv.addn t0, t1, t2, 16246# CHECK-ENCODING: [0xdb,0x22,0x73,0x20]247# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}248 249cv.addn a0, a1, zero, 31250# CHECK-INSTR: cv.addn a0, a1, zero, 31251# CHECK-ENCODING: [0x5b,0xa5,0x05,0x3e]252# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}253 254cv.subunr t0, t1, t2255# CHECK-INSTR: cv.subunr t0, t1, t2256# CHECK-ENCODING: [0xab,0x32,0x73,0x8a]257# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}258 259cv.subunr a0, a1, a2260# CHECK-INSTR: cv.subunr a0, a1, a2261# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8a]262# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}263 264cv.extbs t0, t1265# CHECK-INSTR: cv.extbs t0, t1266# CHECK-ENCODING: [0xab,0x32,0x03,0x64]267# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}268 269cv.extbs a0, a1270# CHECK-INSTR: cv.extbs a0, a1271# CHECK-ENCODING: [0x2b,0xb5,0x05,0x64]272# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}273 274cv.sleu t0, t1, t2275# CHECK-INSTR: cv.sleu t0, t1, t2276# CHECK-ENCODING: [0xab,0x32,0x73,0x54]277# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}278 279cv.sletu t0, t1, t2280# CHECK-INSTR: cv.sleu t0, t1, t2281# CHECK-ENCODING: [0xab,0x32,0x73,0x54]282# CHECK-NO-EXT: unrecognized instruction mnemonic283 284cv.sleu a0, a1, a2285# CHECK-INSTR: cv.sleu a0, a1, a2286# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x54]287# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}288 289cv.sletu a0, a1, a2290# CHECK-INSTR: cv.sleu a0, a1, a2291# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x54]292# CHECK-NO-EXT: unrecognized instruction mnemonic293 294cv.min t0, t1, t2295# CHECK-INSTR: cv.min t0, t1, t2296# CHECK-ENCODING: [0xab,0x32,0x73,0x56]297# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}298 299cv.min a0, a1, a2300# CHECK-INSTR: cv.min a0, a1, a2301# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x56]302# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}303 304cv.suburnr t0, t1, t2305# CHECK-INSTR: cv.suburnr t0, t1, t2306# CHECK-ENCODING: [0xab,0x32,0x73,0x8e]307# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}308 309cv.suburnr a0, a1, a2310# CHECK-INSTR: cv.suburnr a0, a1, a2311# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8e]312# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}313 314cv.addrnr t0, t1, t2315# CHECK-INSTR: cv.addrnr t0, t1, t2316# CHECK-ENCODING: [0xab,0x32,0x73,0x84]317# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}318 319cv.addrnr a0, a1, a2320# CHECK-INSTR: cv.addrnr a0, a1, a2321# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x84]322# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}323 324cv.exths t0, t1325# CHECK-INSTR: cv.exths t0, t1326# CHECK-ENCODING: [0xab,0x32,0x03,0x60]327# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}328 329cv.exths a0, a1330# CHECK-INSTR: cv.exths a0, a1331# CHECK-ENCODING: [0x2b,0xb5,0x05,0x60]332# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}333 334cv.addrn t0, t1, t2, 0335# CHECK-INSTR: cv.addrn t0, t1, t2, 0336# CHECK-ENCODING: [0xdb,0x22,0x73,0x80]337# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}338 339cv.addrn t0, t1, t2, 16340# CHECK-INSTR: cv.addrn t0, t1, t2, 16341# CHECK-ENCODING: [0xdb,0x22,0x73,0xa0]342# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}343 344cv.addrn a0, a1, zero, 31345# CHECK-INSTR: cv.addrn a0, a1, zero, 31346# CHECK-ENCODING: [0x5b,0xa5,0x05,0xbe]347# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}348 349cv.suburn t0, t1, t2, 0350# CHECK-INSTR: cv.suburn t0, t1, t2, 0351# CHECK-ENCODING: [0xdb,0x32,0x73,0xc0]352# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}353 354cv.suburn t0, t1, t2, 16355# CHECK-INSTR: cv.suburn t0, t1, t2, 16356# CHECK-ENCODING: [0xdb,0x32,0x73,0xe0]357# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}358 359cv.suburn a0, a1, zero, 31360# CHECK-INSTR: cv.suburn a0, a1, zero, 31361# CHECK-ENCODING: [0x5b,0xb5,0x05,0xfe]362# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}363 364cv.addnr t0, t1, t2365# CHECK-INSTR: cv.addnr t0, t1, t2366# CHECK-ENCODING: [0xab,0x32,0x73,0x80]367# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}368 369cv.addnr a0, a1, a2370# CHECK-INSTR: cv.addnr a0, a1, a2371# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x80]372# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}373 374cv.subun t0, t1, t2, 0375# CHECK-INSTR: cv.subun t0, t1, t2, 0376# CHECK-ENCODING: [0xdb,0x32,0x73,0x40]377# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}378 379cv.subun t0, t1, t2, 16380# CHECK-INSTR: cv.subun t0, t1, t2, 16381# CHECK-ENCODING: [0xdb,0x32,0x73,0x60]382# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}383 384cv.subun a0, a1, zero, 31385# CHECK-INSTR: cv.subun a0, a1, zero, 31386# CHECK-ENCODING: [0x5b,0xb5,0x05,0x7e]387# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}388