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1# RUN: llvm-mc -triple=riscv32 --mattr=+xcvsimd -show-encoding %s \2# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR3# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvsimd < %s \4# RUN: | llvm-objdump --mattr=+xcvsimd --no-print-imm-hex -M no-aliases -d -r - \5# RUN: | FileCheck --check-prefix=CHECK-INSTR %s6# RUN: not llvm-mc -triple riscv32 %s 2>&1 \7# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s8 9//===----------------------------------------------------------------------===//10// cv.add.h11//===----------------------------------------------------------------------===//12 13cv.add.h t0, t1, t214# CHECK-INSTR: cv.add.h t0, t1, t215# CHECK-ENCODING: [0xfb,0x02,0x73,0x00]16# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}17 18cv.add.h t3, t4, t519# CHECK-INSTR: cv.add.h t3, t4, t520# CHECK-ENCODING: [0x7b,0x8e,0xee,0x01]21# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}22 23cv.add.h a0, a1, a224# CHECK-INSTR: cv.add.h a0, a1, a225# CHECK-ENCODING: [0x7b,0x85,0xc5,0x00]26# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}27 28cv.add.h s0, s1, s229# CHECK-INSTR: cv.add.h s0, s1, s230# CHECK-ENCODING: [0x7b,0x84,0x24,0x01]31# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}32 33//===----------------------------------------------------------------------===//34// cv.add.b35//===----------------------------------------------------------------------===//36 37cv.add.b t0, t1, t238# CHECK-INSTR: cv.add.b t0, t1, t239# CHECK-ENCODING: [0xfb,0x12,0x73,0x00]40# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}41 42cv.add.b t3, t4, t543# CHECK-INSTR: cv.add.b t3, t4, t544# CHECK-ENCODING: [0x7b,0x9e,0xee,0x01]45# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}46 47cv.add.b a0, a1, a248# CHECK-INSTR: cv.add.b a0, a1, a249# CHECK-ENCODING: [0x7b,0x95,0xc5,0x00]50# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}51 52cv.add.b s0, s1, s253# CHECK-INSTR: cv.add.b s0, s1, s254# CHECK-ENCODING: [0x7b,0x94,0x24,0x01]55# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}56 57//===----------------------------------------------------------------------===//58// cv.add.sc.h59//===----------------------------------------------------------------------===//60 61cv.add.sc.h t0, t1, t262# CHECK-INSTR: cv.add.sc.h t0, t1, t263# CHECK-ENCODING: [0xfb,0x42,0x73,0x00]64# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}65 66cv.add.sc.h t3, t4, t567# CHECK-INSTR: cv.add.sc.h t3, t4, t568# CHECK-ENCODING: [0x7b,0xce,0xee,0x01]69# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}70 71cv.add.sc.h a0, a1, a272# CHECK-INSTR: cv.add.sc.h a0, a1, a273# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x00]74# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}75 76cv.add.sc.h s0, s1, s277# CHECK-INSTR: cv.add.sc.h s0, s1, s278# CHECK-ENCODING: [0x7b,0xc4,0x24,0x01]79# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}80 81//===----------------------------------------------------------------------===//82// cv.add.sc.b83//===----------------------------------------------------------------------===//84 85cv.add.sc.b t0, t1, t286# CHECK-INSTR: cv.add.sc.b t0, t1, t287# CHECK-ENCODING: [0xfb,0x52,0x73,0x00]88# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}89 90cv.add.sc.b t3, t4, t591# CHECK-INSTR: cv.add.sc.b t3, t4, t592# CHECK-ENCODING: [0x7b,0xde,0xee,0x01]93# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}94 95cv.add.sc.b a0, a1, a296# CHECK-INSTR: cv.add.sc.b a0, a1, a297# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x00]98# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}99 100cv.add.sc.b s0, s1, s2101# CHECK-INSTR: cv.add.sc.b s0, s1, s2102# CHECK-ENCODING: [0x7b,0xd4,0x24,0x01]103# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}104 105//===----------------------------------------------------------------------===//106// cv.add.sci.h107//===----------------------------------------------------------------------===//108 109cv.add.sci.h t0, t1, 0110# CHECK-INSTR: cv.add.sci.h t0, t1, 0111# CHECK-ENCODING: [0xfb,0x62,0x03,0x00]112# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}113 114cv.add.sci.h t3, t4, -32115# CHECK-INSTR: cv.add.sci.h t3, t4, -32116# CHECK-ENCODING: [0x7b,0xee,0x0e,0x01]117# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}118 119cv.add.sci.h a0, a1, 7120# CHECK-INSTR: cv.add.sci.h a0, a1, 7121# CHECK-ENCODING: [0x7b,0xe5,0x35,0x02]122# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}123 124cv.add.sci.h s0, s1, -1125# CHECK-INSTR: cv.add.sci.h s0, s1, -1126# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x03]127# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}128 129//===----------------------------------------------------------------------===//130// cv.add.sci.b131//===----------------------------------------------------------------------===//132 133cv.add.sci.b t0, t1, 0134# CHECK-INSTR: cv.add.sci.b t0, t1, 0135# CHECK-ENCODING: [0xfb,0x72,0x03,0x00]136# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}137 138cv.add.sci.b t3, t4, -32139# CHECK-INSTR: cv.add.sci.b t3, t4, -32140# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x01]141# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}142 143cv.add.sci.b a0, a1, 7144# CHECK-INSTR: cv.add.sci.b a0, a1, 7145# CHECK-ENCODING: [0x7b,0xf5,0x35,0x02]146# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}147 148cv.add.sci.b s0, s1, -1149# CHECK-INSTR: cv.add.sci.b s0, s1, -1150# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x03]151# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}152 153//===----------------------------------------------------------------------===//154// cv.sub.h155//===----------------------------------------------------------------------===//156 157cv.sub.h t0, t1, t2158# CHECK-INSTR: cv.sub.h t0, t1, t2159# CHECK-ENCODING: [0xfb,0x02,0x73,0x08]160# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}161 162cv.sub.h t3, t4, t5163# CHECK-INSTR: cv.sub.h t3, t4, t5164# CHECK-ENCODING: [0x7b,0x8e,0xee,0x09]165# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}166 167cv.sub.h a0, a1, a2168# CHECK-INSTR: cv.sub.h a0, a1, a2169# CHECK-ENCODING: [0x7b,0x85,0xc5,0x08]170# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}171 172cv.sub.h s0, s1, s2173# CHECK-INSTR: cv.sub.h s0, s1, s2174# CHECK-ENCODING: [0x7b,0x84,0x24,0x09]175# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}176 177//===----------------------------------------------------------------------===//178// cv.sub.b179//===----------------------------------------------------------------------===//180 181cv.sub.b t0, t1, t2182# CHECK-INSTR: cv.sub.b t0, t1, t2183# CHECK-ENCODING: [0xfb,0x12,0x73,0x08]184# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}185 186cv.sub.b t3, t4, t5187# CHECK-INSTR: cv.sub.b t3, t4, t5188# CHECK-ENCODING: [0x7b,0x9e,0xee,0x09]189# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}190 191cv.sub.b a0, a1, a2192# CHECK-INSTR: cv.sub.b a0, a1, a2193# CHECK-ENCODING: [0x7b,0x95,0xc5,0x08]194# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}195 196cv.sub.b s0, s1, s2197# CHECK-INSTR: cv.sub.b s0, s1, s2198# CHECK-ENCODING: [0x7b,0x94,0x24,0x09]199# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}200 201//===----------------------------------------------------------------------===//202// cv.sub.sc.h203//===----------------------------------------------------------------------===//204 205cv.sub.sc.h t0, t1, t2206# CHECK-INSTR: cv.sub.sc.h t0, t1, t2207# CHECK-ENCODING: [0xfb,0x42,0x73,0x08]208# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}209 210cv.sub.sc.h t3, t4, t5211# CHECK-INSTR: cv.sub.sc.h t3, t4, t5212# CHECK-ENCODING: [0x7b,0xce,0xee,0x09]213# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}214 215cv.sub.sc.h a0, a1, a2216# CHECK-INSTR: cv.sub.sc.h a0, a1, a2217# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x08]218# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}219 220cv.sub.sc.h s0, s1, s2221# CHECK-INSTR: cv.sub.sc.h s0, s1, s2222# CHECK-ENCODING: [0x7b,0xc4,0x24,0x09]223# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}224 225//===----------------------------------------------------------------------===//226// cv.sub.sc.b227//===----------------------------------------------------------------------===//228 229cv.sub.sc.b t0, t1, t2230# CHECK-INSTR: cv.sub.sc.b t0, t1, t2231# CHECK-ENCODING: [0xfb,0x52,0x73,0x08]232# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}233 234cv.sub.sc.b t3, t4, t5235# CHECK-INSTR: cv.sub.sc.b t3, t4, t5236# CHECK-ENCODING: [0x7b,0xde,0xee,0x09]237# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}238 239cv.sub.sc.b a0, a1, a2240# CHECK-INSTR: cv.sub.sc.b a0, a1, a2241# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x08]242# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}243 244cv.sub.sc.b s0, s1, s2245# CHECK-INSTR: cv.sub.sc.b s0, s1, s2246# CHECK-ENCODING: [0x7b,0xd4,0x24,0x09]247# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}248 249//===----------------------------------------------------------------------===//250// cv.sub.sci.h251//===----------------------------------------------------------------------===//252 253cv.sub.sci.h t0, t1, 0254# CHECK-INSTR: cv.sub.sci.h t0, t1, 0255# CHECK-ENCODING: [0xfb,0x62,0x03,0x08]256# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}257 258cv.sub.sci.h t3, t4, -32259# CHECK-INSTR: cv.sub.sci.h t3, t4, -32260# CHECK-ENCODING: [0x7b,0xee,0x0e,0x09]261# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}262 263cv.sub.sci.h a0, a1, 7264# CHECK-INSTR: cv.sub.sci.h a0, a1, 7265# CHECK-ENCODING: [0x7b,0xe5,0x35,0x0a]266# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}267 268cv.sub.sci.h s0, s1, -1269# CHECK-INSTR: cv.sub.sci.h s0, s1, -1270# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x0b]271# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}272 273//===----------------------------------------------------------------------===//274// cv.sub.sci.b275//===----------------------------------------------------------------------===//276 277cv.sub.sci.b t0, t1, 0278# CHECK-INSTR: cv.sub.sci.b t0, t1, 0279# CHECK-ENCODING: [0xfb,0x72,0x03,0x08]280# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}281 282cv.sub.sci.b t3, t4, -32283# CHECK-INSTR: cv.sub.sci.b t3, t4, -32284# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x09]285# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}286 287cv.sub.sci.b a0, a1, 7288# CHECK-INSTR: cv.sub.sci.b a0, a1, 7289# CHECK-ENCODING: [0x7b,0xf5,0x35,0x0a]290# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}291 292cv.sub.sci.b s0, s1, -1293# CHECK-INSTR: cv.sub.sci.b s0, s1, -1294# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x0b]295# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}296 297//===----------------------------------------------------------------------===//298// cv.avg.h299//===----------------------------------------------------------------------===//300 301cv.avg.h t0, t1, t2302# CHECK-INSTR: cv.avg.h t0, t1, t2303# CHECK-ENCODING: [0xfb,0x02,0x73,0x10]304# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}305 306cv.avg.h t3, t4, t5307# CHECK-INSTR: cv.avg.h t3, t4, t5308# CHECK-ENCODING: [0x7b,0x8e,0xee,0x11]309# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}310 311cv.avg.h a0, a1, a2312# CHECK-INSTR: cv.avg.h a0, a1, a2313# CHECK-ENCODING: [0x7b,0x85,0xc5,0x10]314# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}315 316cv.avg.h s0, s1, s2317# CHECK-INSTR: cv.avg.h s0, s1, s2318# CHECK-ENCODING: [0x7b,0x84,0x24,0x11]319# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}320 321//===----------------------------------------------------------------------===//322// cv.avg.b323//===----------------------------------------------------------------------===//324 325cv.avg.b t0, t1, t2326# CHECK-INSTR: cv.avg.b t0, t1, t2327# CHECK-ENCODING: [0xfb,0x12,0x73,0x10]328# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}329 330cv.avg.b t3, t4, t5331# CHECK-INSTR: cv.avg.b t3, t4, t5332# CHECK-ENCODING: [0x7b,0x9e,0xee,0x11]333# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}334 335cv.avg.b a0, a1, a2336# CHECK-INSTR: cv.avg.b a0, a1, a2337# CHECK-ENCODING: [0x7b,0x95,0xc5,0x10]338# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}339 340cv.avg.b s0, s1, s2341# CHECK-INSTR: cv.avg.b s0, s1, s2342# CHECK-ENCODING: [0x7b,0x94,0x24,0x11]343# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}344 345//===----------------------------------------------------------------------===//346// cv.avg.sc.h347//===----------------------------------------------------------------------===//348 349cv.avg.sc.h t0, t1, t2350# CHECK-INSTR: cv.avg.sc.h t0, t1, t2351# CHECK-ENCODING: [0xfb,0x42,0x73,0x10]352# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}353 354cv.avg.sc.h t3, t4, t5355# CHECK-INSTR: cv.avg.sc.h t3, t4, t5356# CHECK-ENCODING: [0x7b,0xce,0xee,0x11]357# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}358 359cv.avg.sc.h a0, a1, a2360# CHECK-INSTR: cv.avg.sc.h a0, a1, a2361# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x10]362# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}363 364cv.avg.sc.h s0, s1, s2365# CHECK-INSTR: cv.avg.sc.h s0, s1, s2366# CHECK-ENCODING: [0x7b,0xc4,0x24,0x11]367# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}368 369//===----------------------------------------------------------------------===//370// cv.avg.sc.b371//===----------------------------------------------------------------------===//372 373cv.avg.sc.b t0, t1, t2374# CHECK-INSTR: cv.avg.sc.b t0, t1, t2375# CHECK-ENCODING: [0xfb,0x52,0x73,0x10]376# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}377 378cv.avg.sc.b t3, t4, t5379# CHECK-INSTR: cv.avg.sc.b t3, t4, t5380# CHECK-ENCODING: [0x7b,0xde,0xee,0x11]381# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}382 383cv.avg.sc.b a0, a1, a2384# CHECK-INSTR: cv.avg.sc.b a0, a1, a2385# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x10]386# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}387 388cv.avg.sc.b s0, s1, s2389# CHECK-INSTR: cv.avg.sc.b s0, s1, s2390# CHECK-ENCODING: [0x7b,0xd4,0x24,0x11]391# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}392 393//===----------------------------------------------------------------------===//394// cv.avg.sci.h395//===----------------------------------------------------------------------===//396 397cv.avg.sci.h t0, t1, 0398# CHECK-INSTR: cv.avg.sci.h t0, t1, 0399# CHECK-ENCODING: [0xfb,0x62,0x03,0x10]400# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}401 402cv.avg.sci.h t3, t4, -32403# CHECK-INSTR: cv.avg.sci.h t3, t4, -32404# CHECK-ENCODING: [0x7b,0xee,0x0e,0x11]405# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}406 407cv.avg.sci.h a0, a1, 7408# CHECK-INSTR: cv.avg.sci.h a0, a1, 7409# CHECK-ENCODING: [0x7b,0xe5,0x35,0x12]410# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}411 412cv.avg.sci.h s0, s1, -1413# CHECK-INSTR: cv.avg.sci.h s0, s1, -1414# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x13]415# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}416 417//===----------------------------------------------------------------------===//418// cv.avg.sci.b419//===----------------------------------------------------------------------===//420 421cv.avg.sci.b t0, t1, 0422# CHECK-INSTR: cv.avg.sci.b t0, t1, 0423# CHECK-ENCODING: [0xfb,0x72,0x03,0x10]424# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}425 426cv.avg.sci.b t3, t4, -32427# CHECK-INSTR: cv.avg.sci.b t3, t4, -32428# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x11]429# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}430 431cv.avg.sci.b a0, a1, 7432# CHECK-INSTR: cv.avg.sci.b a0, a1, 7433# CHECK-ENCODING: [0x7b,0xf5,0x35,0x12]434# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}435 436cv.avg.sci.b s0, s1, -1437# CHECK-INSTR: cv.avg.sci.b s0, s1, -1438# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x13]439# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}440 441//===----------------------------------------------------------------------===//442// cv.avgu.h443//===----------------------------------------------------------------------===//444 445cv.avgu.h t0, t1, t2446# CHECK-INSTR: cv.avgu.h t0, t1, t2447# CHECK-ENCODING: [0xfb,0x02,0x73,0x18]448# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}449 450cv.avgu.h t3, t4, t5451# CHECK-INSTR: cv.avgu.h t3, t4, t5452# CHECK-ENCODING: [0x7b,0x8e,0xee,0x19]453# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}454 455cv.avgu.h a0, a1, a2456# CHECK-INSTR: cv.avgu.h a0, a1, a2457# CHECK-ENCODING: [0x7b,0x85,0xc5,0x18]458# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}459 460cv.avgu.h s0, s1, s2461# CHECK-INSTR: cv.avgu.h s0, s1, s2462# CHECK-ENCODING: [0x7b,0x84,0x24,0x19]463# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}464 465//===----------------------------------------------------------------------===//466// cv.avgu.b467//===----------------------------------------------------------------------===//468 469cv.avgu.b t0, t1, t2470# CHECK-INSTR: cv.avgu.b t0, t1, t2471# CHECK-ENCODING: [0xfb,0x12,0x73,0x18]472# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}473 474cv.avgu.b t3, t4, t5475# CHECK-INSTR: cv.avgu.b t3, t4, t5476# CHECK-ENCODING: [0x7b,0x9e,0xee,0x19]477# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}478 479cv.avgu.b a0, a1, a2480# CHECK-INSTR: cv.avgu.b a0, a1, a2481# CHECK-ENCODING: [0x7b,0x95,0xc5,0x18]482# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}483 484cv.avgu.b s0, s1, s2485# CHECK-INSTR: cv.avgu.b s0, s1, s2486# CHECK-ENCODING: [0x7b,0x94,0x24,0x19]487# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}488 489//===----------------------------------------------------------------------===//490// cv.avgu.sc.h491//===----------------------------------------------------------------------===//492 493cv.avgu.sc.h t0, t1, t2494# CHECK-INSTR: cv.avgu.sc.h t0, t1, t2495# CHECK-ENCODING: [0xfb,0x42,0x73,0x18]496# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}497 498cv.avgu.sc.h t3, t4, t5499# CHECK-INSTR: cv.avgu.sc.h t3, t4, t5500# CHECK-ENCODING: [0x7b,0xce,0xee,0x19]501# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}502 503cv.avgu.sc.h a0, a1, a2504# CHECK-INSTR: cv.avgu.sc.h a0, a1, a2505# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x18]506# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}507 508cv.avgu.sc.h s0, s1, s2509# CHECK-INSTR: cv.avgu.sc.h s0, s1, s2510# CHECK-ENCODING: [0x7b,0xc4,0x24,0x19]511# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}512 513//===----------------------------------------------------------------------===//514// cv.avgu.sc.b515//===----------------------------------------------------------------------===//516 517cv.avgu.sc.b t0, t1, t2518# CHECK-INSTR: cv.avgu.sc.b t0, t1, t2519# CHECK-ENCODING: [0xfb,0x52,0x73,0x18]520# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}521 522cv.avgu.sc.b t3, t4, t5523# CHECK-INSTR: cv.avgu.sc.b t3, t4, t5524# CHECK-ENCODING: [0x7b,0xde,0xee,0x19]525# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}526 527cv.avgu.sc.b a0, a1, a2528# CHECK-INSTR: cv.avgu.sc.b a0, a1, a2529# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x18]530# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}531 532cv.avgu.sc.b s0, s1, s2533# CHECK-INSTR: cv.avgu.sc.b s0, s1, s2534# CHECK-ENCODING: [0x7b,0xd4,0x24,0x19]535# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}536 537//===----------------------------------------------------------------------===//538// cv.avgu.sci.h539//===----------------------------------------------------------------------===//540 541cv.avgu.sci.h t0, t1, 0542# CHECK-INSTR: cv.avgu.sci.h t0, t1, 0543# CHECK-ENCODING: [0xfb,0x62,0x03,0x18]544# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}545 546cv.avgu.sci.h t3, t4, 32547# CHECK-INSTR: cv.avgu.sci.h t3, t4, 32548# CHECK-ENCODING: [0x7b,0xee,0x0e,0x19]549# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}550 551cv.avgu.sci.h a0, a1, 7552# CHECK-INSTR: cv.avgu.sci.h a0, a1, 7553# CHECK-ENCODING: [0x7b,0xe5,0x35,0x1a]554# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}555 556cv.avgu.sci.h s0, s1, 63557# CHECK-INSTR: cv.avgu.sci.h s0, s1, 63558# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x1b]559# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}560 561//===----------------------------------------------------------------------===//562// cv.avgu.sci.b563//===----------------------------------------------------------------------===//564 565cv.avgu.sci.b t0, t1, 0566# CHECK-INSTR: cv.avgu.sci.b t0, t1, 0567# CHECK-ENCODING: [0xfb,0x72,0x03,0x18]568# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}569 570cv.avgu.sci.b t3, t4, 32571# CHECK-INSTR: cv.avgu.sci.b t3, t4, 32572# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x19]573# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}574 575cv.avgu.sci.b a0, a1, 7576# CHECK-INSTR: cv.avgu.sci.b a0, a1, 7577# CHECK-ENCODING: [0x7b,0xf5,0x35,0x1a]578# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}579 580cv.avgu.sci.b s0, s1, 63581# CHECK-INSTR: cv.avgu.sci.b s0, s1, 63582# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x1b]583# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}584 585//===----------------------------------------------------------------------===//586// cv.min.h587//===----------------------------------------------------------------------===//588 589cv.min.h t0, t1, t2590# CHECK-INSTR: cv.min.h t0, t1, t2591# CHECK-ENCODING: [0xfb,0x02,0x73,0x20]592# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}593 594cv.min.h t3, t4, t5595# CHECK-INSTR: cv.min.h t3, t4, t5596# CHECK-ENCODING: [0x7b,0x8e,0xee,0x21]597# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}598 599cv.min.h a0, a1, a2600# CHECK-INSTR: cv.min.h a0, a1, a2601# CHECK-ENCODING: [0x7b,0x85,0xc5,0x20]602# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}603 604cv.min.h s0, s1, s2605# CHECK-INSTR: cv.min.h s0, s1, s2606# CHECK-ENCODING: [0x7b,0x84,0x24,0x21]607# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}608 609//===----------------------------------------------------------------------===//610// cv.min.b611//===----------------------------------------------------------------------===//612 613cv.min.b t0, t1, t2614# CHECK-INSTR: cv.min.b t0, t1, t2615# CHECK-ENCODING: [0xfb,0x12,0x73,0x20]616# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}617 618cv.min.b t3, t4, t5619# CHECK-INSTR: cv.min.b t3, t4, t5620# CHECK-ENCODING: [0x7b,0x9e,0xee,0x21]621# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}622 623cv.min.b a0, a1, a2624# CHECK-INSTR: cv.min.b a0, a1, a2625# CHECK-ENCODING: [0x7b,0x95,0xc5,0x20]626# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}627 628cv.min.b s0, s1, s2629# CHECK-INSTR: cv.min.b s0, s1, s2630# CHECK-ENCODING: [0x7b,0x94,0x24,0x21]631# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}632 633//===----------------------------------------------------------------------===//634// cv.min.sc.h635//===----------------------------------------------------------------------===//636 637cv.min.sc.h t0, t1, t2638# CHECK-INSTR: cv.min.sc.h t0, t1, t2639# CHECK-ENCODING: [0xfb,0x42,0x73,0x20]640# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}641 642cv.min.sc.h t3, t4, t5643# CHECK-INSTR: cv.min.sc.h t3, t4, t5644# CHECK-ENCODING: [0x7b,0xce,0xee,0x21]645# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}646 647cv.min.sc.h a0, a1, a2648# CHECK-INSTR: cv.min.sc.h a0, a1, a2649# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x20]650# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}651 652cv.min.sc.h s0, s1, s2653# CHECK-INSTR: cv.min.sc.h s0, s1, s2654# CHECK-ENCODING: [0x7b,0xc4,0x24,0x21]655# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}656 657//===----------------------------------------------------------------------===//658// cv.min.sc.b659//===----------------------------------------------------------------------===//660 661cv.min.sc.b t0, t1, t2662# CHECK-INSTR: cv.min.sc.b t0, t1, t2663# CHECK-ENCODING: [0xfb,0x52,0x73,0x20]664# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}665 666cv.min.sc.b t3, t4, t5667# CHECK-INSTR: cv.min.sc.b t3, t4, t5668# CHECK-ENCODING: [0x7b,0xde,0xee,0x21]669# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}670 671cv.min.sc.b a0, a1, a2672# CHECK-INSTR: cv.min.sc.b a0, a1, a2673# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x20]674# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}675 676cv.min.sc.b s0, s1, s2677# CHECK-INSTR: cv.min.sc.b s0, s1, s2678# CHECK-ENCODING: [0x7b,0xd4,0x24,0x21]679# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}680 681//===----------------------------------------------------------------------===//682// cv.min.sci.h683//===----------------------------------------------------------------------===//684 685cv.min.sci.h t0, t1, 0686# CHECK-INSTR: cv.min.sci.h t0, t1, 0687# CHECK-ENCODING: [0xfb,0x62,0x03,0x20]688# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}689 690cv.min.sci.h t3, t4, -32691# CHECK-INSTR: cv.min.sci.h t3, t4, -32692# CHECK-ENCODING: [0x7b,0xee,0x0e,0x21]693# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}694 695cv.min.sci.h a0, a1, 7696# CHECK-INSTR: cv.min.sci.h a0, a1, 7697# CHECK-ENCODING: [0x7b,0xe5,0x35,0x22]698# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}699 700cv.min.sci.h s0, s1, -1701# CHECK-INSTR: cv.min.sci.h s0, s1, -1702# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x23]703# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}704 705//===----------------------------------------------------------------------===//706// cv.min.sci.b707//===----------------------------------------------------------------------===//708 709cv.min.sci.b t0, t1, 0710# CHECK-INSTR: cv.min.sci.b t0, t1, 0711# CHECK-ENCODING: [0xfb,0x72,0x03,0x20]712# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}713 714cv.min.sci.b t3, t4, -32715# CHECK-INSTR: cv.min.sci.b t3, t4, -32716# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x21]717# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}718 719cv.min.sci.b a0, a1, 7720# CHECK-INSTR: cv.min.sci.b a0, a1, 7721# CHECK-ENCODING: [0x7b,0xf5,0x35,0x22]722# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}723 724cv.min.sci.b s0, s1, -1725# CHECK-INSTR: cv.min.sci.b s0, s1, -1726# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x23]727# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}728 729//===----------------------------------------------------------------------===//730// cv.minu.h731//===----------------------------------------------------------------------===//732 733cv.minu.h t0, t1, t2734# CHECK-INSTR: cv.minu.h t0, t1, t2735# CHECK-ENCODING: [0xfb,0x02,0x73,0x28]736# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}737 738cv.minu.h t3, t4, t5739# CHECK-INSTR: cv.minu.h t3, t4, t5740# CHECK-ENCODING: [0x7b,0x8e,0xee,0x29]741# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}742 743cv.minu.h a0, a1, a2744# CHECK-INSTR: cv.minu.h a0, a1, a2745# CHECK-ENCODING: [0x7b,0x85,0xc5,0x28]746# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}747 748cv.minu.h s0, s1, s2749# CHECK-INSTR: cv.minu.h s0, s1, s2750# CHECK-ENCODING: [0x7b,0x84,0x24,0x29]751# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}752 753//===----------------------------------------------------------------------===//754// cv.minu.b755//===----------------------------------------------------------------------===//756 757cv.minu.b t0, t1, t2758# CHECK-INSTR: cv.minu.b t0, t1, t2759# CHECK-ENCODING: [0xfb,0x12,0x73,0x28]760# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}761 762cv.minu.b t3, t4, t5763# CHECK-INSTR: cv.minu.b t3, t4, t5764# CHECK-ENCODING: [0x7b,0x9e,0xee,0x29]765# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}766 767cv.minu.b a0, a1, a2768# CHECK-INSTR: cv.minu.b a0, a1, a2769# CHECK-ENCODING: [0x7b,0x95,0xc5,0x28]770# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}771 772cv.minu.b s0, s1, s2773# CHECK-INSTR: cv.minu.b s0, s1, s2774# CHECK-ENCODING: [0x7b,0x94,0x24,0x29]775# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}776 777//===----------------------------------------------------------------------===//778// cv.minu.sc.h779//===----------------------------------------------------------------------===//780 781cv.minu.sc.h t0, t1, t2782# CHECK-INSTR: cv.minu.sc.h t0, t1, t2783# CHECK-ENCODING: [0xfb,0x42,0x73,0x28]784# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}785 786cv.minu.sc.h t3, t4, t5787# CHECK-INSTR: cv.minu.sc.h t3, t4, t5788# CHECK-ENCODING: [0x7b,0xce,0xee,0x29]789# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}790 791cv.minu.sc.h a0, a1, a2792# CHECK-INSTR: cv.minu.sc.h a0, a1, a2793# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x28]794# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}795 796cv.minu.sc.h s0, s1, s2797# CHECK-INSTR: cv.minu.sc.h s0, s1, s2798# CHECK-ENCODING: [0x7b,0xc4,0x24,0x29]799# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}800 801//===----------------------------------------------------------------------===//802// cv.minu.sc.b803//===----------------------------------------------------------------------===//804 805cv.minu.sc.b t0, t1, t2806# CHECK-INSTR: cv.minu.sc.b t0, t1, t2807# CHECK-ENCODING: [0xfb,0x52,0x73,0x28]808# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}809 810cv.minu.sc.b t3, t4, t5811# CHECK-INSTR: cv.minu.sc.b t3, t4, t5812# CHECK-ENCODING: [0x7b,0xde,0xee,0x29]813# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}814 815cv.minu.sc.b a0, a1, a2816# CHECK-INSTR: cv.minu.sc.b a0, a1, a2817# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x28]818# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}819 820cv.minu.sc.b s0, s1, s2821# CHECK-INSTR: cv.minu.sc.b s0, s1, s2822# CHECK-ENCODING: [0x7b,0xd4,0x24,0x29]823# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}824 825//===----------------------------------------------------------------------===//826// cv.minu.sci.h827//===----------------------------------------------------------------------===//828 829cv.minu.sci.h t0, t1, 0830# CHECK-INSTR: cv.minu.sci.h t0, t1, 0831# CHECK-ENCODING: [0xfb,0x62,0x03,0x28]832# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}833 834cv.minu.sci.h t3, t4, 32835# CHECK-INSTR: cv.minu.sci.h t3, t4, 32836# CHECK-ENCODING: [0x7b,0xee,0x0e,0x29]837# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}838 839cv.minu.sci.h a0, a1, 7840# CHECK-INSTR: cv.minu.sci.h a0, a1, 7841# CHECK-ENCODING: [0x7b,0xe5,0x35,0x2a]842# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}843 844cv.minu.sci.h s0, s1, 63845# CHECK-INSTR: cv.minu.sci.h s0, s1, 63846# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x2b]847# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}848 849//===----------------------------------------------------------------------===//850// cv.minu.sci.b851//===----------------------------------------------------------------------===//852 853cv.minu.sci.b t0, t1, 0854# CHECK-INSTR: cv.minu.sci.b t0, t1, 0855# CHECK-ENCODING: [0xfb,0x72,0x03,0x28]856# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}857 858cv.minu.sci.b t3, t4, 32859# CHECK-INSTR: cv.minu.sci.b t3, t4, 32860# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x29]861# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}862 863cv.minu.sci.b a0, a1, 7864# CHECK-INSTR: cv.minu.sci.b a0, a1, 7865# CHECK-ENCODING: [0x7b,0xf5,0x35,0x2a]866# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}867 868cv.minu.sci.b s0, s1, 63869# CHECK-INSTR: cv.minu.sci.b s0, s1, 63870# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x2b]871# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}872 873//===----------------------------------------------------------------------===//874// cv.max.h875//===----------------------------------------------------------------------===//876 877cv.max.h t0, t1, t2878# CHECK-INSTR: cv.max.h t0, t1, t2879# CHECK-ENCODING: [0xfb,0x02,0x73,0x30]880# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}881 882cv.max.h t3, t4, t5883# CHECK-INSTR: cv.max.h t3, t4, t5884# CHECK-ENCODING: [0x7b,0x8e,0xee,0x31]885# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}886 887cv.max.h a0, a1, a2888# CHECK-INSTR: cv.max.h a0, a1, a2889# CHECK-ENCODING: [0x7b,0x85,0xc5,0x30]890# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}891 892cv.max.h s0, s1, s2893# CHECK-INSTR: cv.max.h s0, s1, s2894# CHECK-ENCODING: [0x7b,0x84,0x24,0x31]895# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}896 897//===----------------------------------------------------------------------===//898// cv.max.b899//===----------------------------------------------------------------------===//900 901cv.max.b t0, t1, t2902# CHECK-INSTR: cv.max.b t0, t1, t2903# CHECK-ENCODING: [0xfb,0x12,0x73,0x30]904# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}905 906cv.max.b t3, t4, t5907# CHECK-INSTR: cv.max.b t3, t4, t5908# CHECK-ENCODING: [0x7b,0x9e,0xee,0x31]909# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}910 911cv.max.b a0, a1, a2912# CHECK-INSTR: cv.max.b a0, a1, a2913# CHECK-ENCODING: [0x7b,0x95,0xc5,0x30]914# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}915 916cv.max.b s0, s1, s2917# CHECK-INSTR: cv.max.b s0, s1, s2918# CHECK-ENCODING: [0x7b,0x94,0x24,0x31]919# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}920 921//===----------------------------------------------------------------------===//922// cv.max.sc.h923//===----------------------------------------------------------------------===//924 925cv.max.sc.h t0, t1, t2926# CHECK-INSTR: cv.max.sc.h t0, t1, t2927# CHECK-ENCODING: [0xfb,0x42,0x73,0x30]928# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}929 930cv.max.sc.h t3, t4, t5931# CHECK-INSTR: cv.max.sc.h t3, t4, t5932# CHECK-ENCODING: [0x7b,0xce,0xee,0x31]933# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}934 935cv.max.sc.h a0, a1, a2936# CHECK-INSTR: cv.max.sc.h a0, a1, a2937# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x30]938# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}939 940cv.max.sc.h s0, s1, s2941# CHECK-INSTR: cv.max.sc.h s0, s1, s2942# CHECK-ENCODING: [0x7b,0xc4,0x24,0x31]943# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}944 945//===----------------------------------------------------------------------===//946// cv.max.sc.b947//===----------------------------------------------------------------------===//948 949cv.max.sc.b t0, t1, t2950# CHECK-INSTR: cv.max.sc.b t0, t1, t2951# CHECK-ENCODING: [0xfb,0x52,0x73,0x30]952# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}953 954cv.max.sc.b t3, t4, t5955# CHECK-INSTR: cv.max.sc.b t3, t4, t5956# CHECK-ENCODING: [0x7b,0xde,0xee,0x31]957# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}958 959cv.max.sc.b a0, a1, a2960# CHECK-INSTR: cv.max.sc.b a0, a1, a2961# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x30]962# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}963 964cv.max.sc.b s0, s1, s2965# CHECK-INSTR: cv.max.sc.b s0, s1, s2966# CHECK-ENCODING: [0x7b,0xd4,0x24,0x31]967# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}968 969//===----------------------------------------------------------------------===//970// cv.max.sci.h971//===----------------------------------------------------------------------===//972 973cv.max.sci.h t0, t1, 0974# CHECK-INSTR: cv.max.sci.h t0, t1, 0975# CHECK-ENCODING: [0xfb,0x62,0x03,0x30]976# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}977 978cv.max.sci.h t3, t4, -32979# CHECK-INSTR: cv.max.sci.h t3, t4, -32980# CHECK-ENCODING: [0x7b,0xee,0x0e,0x31]981# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}982 983cv.max.sci.h a0, a1, 7984# CHECK-INSTR: cv.max.sci.h a0, a1, 7985# CHECK-ENCODING: [0x7b,0xe5,0x35,0x32]986# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}987 988cv.max.sci.h s0, s1, -1989# CHECK-INSTR: cv.max.sci.h s0, s1, -1990# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x33]991# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}992 993//===----------------------------------------------------------------------===//994// cv.max.sci.b995//===----------------------------------------------------------------------===//996 997cv.max.sci.b t0, t1, 0998# CHECK-INSTR: cv.max.sci.b t0, t1, 0999# CHECK-ENCODING: [0xfb,0x72,0x03,0x30]1000# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1001 1002cv.max.sci.b t3, t4, -321003# CHECK-INSTR: cv.max.sci.b t3, t4, -321004# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x31]1005# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1006 1007cv.max.sci.b a0, a1, 71008# CHECK-INSTR: cv.max.sci.b a0, a1, 71009# CHECK-ENCODING: [0x7b,0xf5,0x35,0x32]1010# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1011 1012cv.max.sci.b s0, s1, -11013# CHECK-INSTR: cv.max.sci.b s0, s1, -11014# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x33]1015# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1016 1017//===----------------------------------------------------------------------===//1018// cv.maxu.h1019//===----------------------------------------------------------------------===//1020 1021cv.maxu.h t0, t1, t21022# CHECK-INSTR: cv.maxu.h t0, t1, t21023# CHECK-ENCODING: [0xfb,0x02,0x73,0x38]1024# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1025 1026cv.maxu.h t3, t4, t51027# CHECK-INSTR: cv.maxu.h t3, t4, t51028# CHECK-ENCODING: [0x7b,0x8e,0xee,0x39]1029# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1030 1031cv.maxu.h a0, a1, a21032# CHECK-INSTR: cv.maxu.h a0, a1, a21033# CHECK-ENCODING: [0x7b,0x85,0xc5,0x38]1034# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1035 1036cv.maxu.h s0, s1, s21037# CHECK-INSTR: cv.maxu.h s0, s1, s21038# CHECK-ENCODING: [0x7b,0x84,0x24,0x39]1039# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1040 1041//===----------------------------------------------------------------------===//1042// cv.maxu.b1043//===----------------------------------------------------------------------===//1044 1045cv.maxu.b t0, t1, t21046# CHECK-INSTR: cv.maxu.b t0, t1, t21047# CHECK-ENCODING: [0xfb,0x12,0x73,0x38]1048# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1049 1050cv.maxu.b t3, t4, t51051# CHECK-INSTR: cv.maxu.b t3, t4, t51052# CHECK-ENCODING: [0x7b,0x9e,0xee,0x39]1053# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1054 1055cv.maxu.b a0, a1, a21056# CHECK-INSTR: cv.maxu.b a0, a1, a21057# CHECK-ENCODING: [0x7b,0x95,0xc5,0x38]1058# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1059 1060cv.maxu.b s0, s1, s21061# CHECK-INSTR: cv.maxu.b s0, s1, s21062# CHECK-ENCODING: [0x7b,0x94,0x24,0x39]1063# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1064 1065//===----------------------------------------------------------------------===//1066// cv.maxu.sc.h1067//===----------------------------------------------------------------------===//1068 1069cv.maxu.sc.h t0, t1, t21070# CHECK-INSTR: cv.maxu.sc.h t0, t1, t21071# CHECK-ENCODING: [0xfb,0x42,0x73,0x38]1072# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1073 1074cv.maxu.sc.h t3, t4, t51075# CHECK-INSTR: cv.maxu.sc.h t3, t4, t51076# CHECK-ENCODING: [0x7b,0xce,0xee,0x39]1077# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1078 1079cv.maxu.sc.h a0, a1, a21080# CHECK-INSTR: cv.maxu.sc.h a0, a1, a21081# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x38]1082# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1083 1084cv.maxu.sc.h s0, s1, s21085# CHECK-INSTR: cv.maxu.sc.h s0, s1, s21086# CHECK-ENCODING: [0x7b,0xc4,0x24,0x39]1087# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1088 1089//===----------------------------------------------------------------------===//1090// cv.maxu.sc.b1091//===----------------------------------------------------------------------===//1092 1093cv.maxu.sc.b t0, t1, t21094# CHECK-INSTR: cv.maxu.sc.b t0, t1, t21095# CHECK-ENCODING: [0xfb,0x52,0x73,0x38]1096# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1097 1098cv.maxu.sc.b t3, t4, t51099# CHECK-INSTR: cv.maxu.sc.b t3, t4, t51100# CHECK-ENCODING: [0x7b,0xde,0xee,0x39]1101# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1102 1103cv.maxu.sc.b a0, a1, a21104# CHECK-INSTR: cv.maxu.sc.b a0, a1, a21105# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x38]1106# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1107 1108cv.maxu.sc.b s0, s1, s21109# CHECK-INSTR: cv.maxu.sc.b s0, s1, s21110# CHECK-ENCODING: [0x7b,0xd4,0x24,0x39]1111# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1112 1113//===----------------------------------------------------------------------===//1114// cv.maxu.sci.h1115//===----------------------------------------------------------------------===//1116 1117cv.maxu.sci.h t0, t1, 01118# CHECK-INSTR: cv.maxu.sci.h t0, t1, 01119# CHECK-ENCODING: [0xfb,0x62,0x03,0x38]1120# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1121 1122cv.maxu.sci.h t3, t4, 321123# CHECK-INSTR: cv.maxu.sci.h t3, t4, 321124# CHECK-ENCODING: [0x7b,0xee,0x0e,0x39]1125# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1126 1127cv.maxu.sci.h a0, a1, 71128# CHECK-INSTR: cv.maxu.sci.h a0, a1, 71129# CHECK-ENCODING: [0x7b,0xe5,0x35,0x3a]1130# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1131 1132cv.maxu.sci.h s0, s1, 631133# CHECK-INSTR: cv.maxu.sci.h s0, s1, 631134# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x3b]1135# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1136 1137//===----------------------------------------------------------------------===//1138// cv.maxu.sci.b1139//===----------------------------------------------------------------------===//1140 1141cv.maxu.sci.b t0, t1, 01142# CHECK-INSTR: cv.maxu.sci.b t0, t1, 01143# CHECK-ENCODING: [0xfb,0x72,0x03,0x38]1144# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1145 1146cv.maxu.sci.b t3, t4, 321147# CHECK-INSTR: cv.maxu.sci.b t3, t4, 321148# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x39]1149# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1150 1151cv.maxu.sci.b a0, a1, 71152# CHECK-INSTR: cv.maxu.sci.b a0, a1, 71153# CHECK-ENCODING: [0x7b,0xf5,0x35,0x3a]1154# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1155 1156cv.maxu.sci.b s0, s1, 631157# CHECK-INSTR: cv.maxu.sci.b s0, s1, 631158# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x3b]1159# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1160 1161//===----------------------------------------------------------------------===//1162// cv.srl.h1163//===----------------------------------------------------------------------===//1164 1165cv.srl.h t0, t1, t21166# CHECK-INSTR: cv.srl.h t0, t1, t21167# CHECK-ENCODING: [0xfb,0x02,0x73,0x40]1168# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1169 1170cv.srl.h t3, t4, t51171# CHECK-INSTR: cv.srl.h t3, t4, t51172# CHECK-ENCODING: [0x7b,0x8e,0xee,0x41]1173# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1174 1175cv.srl.h a0, a1, a21176# CHECK-INSTR: cv.srl.h a0, a1, a21177# CHECK-ENCODING: [0x7b,0x85,0xc5,0x40]1178# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1179 1180cv.srl.h s0, s1, s21181# CHECK-INSTR: cv.srl.h s0, s1, s21182# CHECK-ENCODING: [0x7b,0x84,0x24,0x41]1183# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1184 1185//===----------------------------------------------------------------------===//1186// cv.srl.b1187//===----------------------------------------------------------------------===//1188 1189cv.srl.b t0, t1, t21190# CHECK-INSTR: cv.srl.b t0, t1, t21191# CHECK-ENCODING: [0xfb,0x12,0x73,0x40]1192# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1193 1194cv.srl.b t3, t4, t51195# CHECK-INSTR: cv.srl.b t3, t4, t51196# CHECK-ENCODING: [0x7b,0x9e,0xee,0x41]1197# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1198 1199cv.srl.b a0, a1, a21200# CHECK-INSTR: cv.srl.b a0, a1, a21201# CHECK-ENCODING: [0x7b,0x95,0xc5,0x40]1202# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1203 1204cv.srl.b s0, s1, s21205# CHECK-INSTR: cv.srl.b s0, s1, s21206# CHECK-ENCODING: [0x7b,0x94,0x24,0x41]1207# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1208 1209//===----------------------------------------------------------------------===//1210// cv.srl.sc.h1211//===----------------------------------------------------------------------===//1212 1213cv.srl.sc.h t0, t1, t21214# CHECK-INSTR: cv.srl.sc.h t0, t1, t21215# CHECK-ENCODING: [0xfb,0x42,0x73,0x40]1216# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1217 1218cv.srl.sc.h t3, t4, t51219# CHECK-INSTR: cv.srl.sc.h t3, t4, t51220# CHECK-ENCODING: [0x7b,0xce,0xee,0x41]1221# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1222 1223cv.srl.sc.h a0, a1, a21224# CHECK-INSTR: cv.srl.sc.h a0, a1, a21225# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x40]1226# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1227 1228cv.srl.sc.h s0, s1, s21229# CHECK-INSTR: cv.srl.sc.h s0, s1, s21230# CHECK-ENCODING: [0x7b,0xc4,0x24,0x41]1231# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1232 1233//===----------------------------------------------------------------------===//1234// cv.srl.sc.b1235//===----------------------------------------------------------------------===//1236 1237cv.srl.sc.b t0, t1, t21238# CHECK-INSTR: cv.srl.sc.b t0, t1, t21239# CHECK-ENCODING: [0xfb,0x52,0x73,0x40]1240# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1241 1242cv.srl.sc.b t3, t4, t51243# CHECK-INSTR: cv.srl.sc.b t3, t4, t51244# CHECK-ENCODING: [0x7b,0xde,0xee,0x41]1245# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1246 1247cv.srl.sc.b a0, a1, a21248# CHECK-INSTR: cv.srl.sc.b a0, a1, a21249# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x40]1250# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1251 1252cv.srl.sc.b s0, s1, s21253# CHECK-INSTR: cv.srl.sc.b s0, s1, s21254# CHECK-ENCODING: [0x7b,0xd4,0x24,0x41]1255# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1256 1257//===----------------------------------------------------------------------===//1258// cv.srl.sci.h1259//===----------------------------------------------------------------------===//1260 1261cv.srl.sci.h t0, t1, 01262# CHECK-INSTR: cv.srl.sci.h t0, t1, 01263# CHECK-ENCODING: [0xfb,0x62,0x03,0x40]1264# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1265 1266cv.srl.sci.h t3, t4, 01267# CHECK-INSTR: cv.srl.sci.h t3, t4, 01268# CHECK-ENCODING: [0x7b,0xee,0x0e,0x40]1269# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1270 1271cv.srl.sci.h a0, a1, 71272# CHECK-INSTR: cv.srl.sci.h a0, a1, 71273# CHECK-ENCODING: [0x7b,0xe5,0x35,0x42]1274# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1275 1276cv.srl.sci.h s0, s1, 151277# CHECK-INSTR: cv.srl.sci.h s0, s1, 151278# CHECK-ENCODING: [0x7b,0xe4,0x74,0x42]1279# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1280 1281//===----------------------------------------------------------------------===//1282// cv.srl.sci.b1283//===----------------------------------------------------------------------===//1284 1285cv.srl.sci.b t0, t1, 01286# CHECK-INSTR: cv.srl.sci.b t0, t1, 01287# CHECK-ENCODING: [0xfb,0x72,0x03,0x40]1288# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1289 1290cv.srl.sci.b t3, t4, 01291# CHECK-INSTR: cv.srl.sci.b t3, t4, 01292# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x40]1293# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1294 1295cv.srl.sci.b a0, a1, 71296# CHECK-INSTR: cv.srl.sci.b a0, a1, 71297# CHECK-ENCODING: [0x7b,0xf5,0x35,0x42]1298# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1299 1300cv.srl.sci.b s0, s1, 71301# CHECK-INSTR: cv.srl.sci.b s0, s1, 71302# CHECK-ENCODING: [0x7b,0xf4,0x34,0x42]1303# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1304 1305//===----------------------------------------------------------------------===//1306// cv.sra.h1307//===----------------------------------------------------------------------===//1308 1309cv.sra.h t0, t1, t21310# CHECK-INSTR: cv.sra.h t0, t1, t21311# CHECK-ENCODING: [0xfb,0x02,0x73,0x48]1312# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1313 1314cv.sra.h t3, t4, t51315# CHECK-INSTR: cv.sra.h t3, t4, t51316# CHECK-ENCODING: [0x7b,0x8e,0xee,0x49]1317# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1318 1319cv.sra.h a0, a1, a21320# CHECK-INSTR: cv.sra.h a0, a1, a21321# CHECK-ENCODING: [0x7b,0x85,0xc5,0x48]1322# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1323 1324cv.sra.h s0, s1, s21325# CHECK-INSTR: cv.sra.h s0, s1, s21326# CHECK-ENCODING: [0x7b,0x84,0x24,0x49]1327# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1328 1329//===----------------------------------------------------------------------===//1330// cv.sra.b1331//===----------------------------------------------------------------------===//1332 1333cv.sra.b t0, t1, t21334# CHECK-INSTR: cv.sra.b t0, t1, t21335# CHECK-ENCODING: [0xfb,0x12,0x73,0x48]1336# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1337 1338cv.sra.b t3, t4, t51339# CHECK-INSTR: cv.sra.b t3, t4, t51340# CHECK-ENCODING: [0x7b,0x9e,0xee,0x49]1341# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1342 1343cv.sra.b a0, a1, a21344# CHECK-INSTR: cv.sra.b a0, a1, a21345# CHECK-ENCODING: [0x7b,0x95,0xc5,0x48]1346# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1347 1348cv.sra.b s0, s1, s21349# CHECK-INSTR: cv.sra.b s0, s1, s21350# CHECK-ENCODING: [0x7b,0x94,0x24,0x49]1351# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1352 1353//===----------------------------------------------------------------------===//1354// cv.sra.sc.h1355//===----------------------------------------------------------------------===//1356 1357cv.sra.sc.h t0, t1, t21358# CHECK-INSTR: cv.sra.sc.h t0, t1, t21359# CHECK-ENCODING: [0xfb,0x42,0x73,0x48]1360# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1361 1362cv.sra.sc.h t3, t4, t51363# CHECK-INSTR: cv.sra.sc.h t3, t4, t51364# CHECK-ENCODING: [0x7b,0xce,0xee,0x49]1365# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1366 1367cv.sra.sc.h a0, a1, a21368# CHECK-INSTR: cv.sra.sc.h a0, a1, a21369# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x48]1370# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1371 1372cv.sra.sc.h s0, s1, s21373# CHECK-INSTR: cv.sra.sc.h s0, s1, s21374# CHECK-ENCODING: [0x7b,0xc4,0x24,0x49]1375# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1376 1377//===----------------------------------------------------------------------===//1378// cv.sra.sc.b1379//===----------------------------------------------------------------------===//1380 1381cv.sra.sc.b t0, t1, t21382# CHECK-INSTR: cv.sra.sc.b t0, t1, t21383# CHECK-ENCODING: [0xfb,0x52,0x73,0x48]1384# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1385 1386cv.sra.sc.b t3, t4, t51387# CHECK-INSTR: cv.sra.sc.b t3, t4, t51388# CHECK-ENCODING: [0x7b,0xde,0xee,0x49]1389# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1390 1391cv.sra.sc.b a0, a1, a21392# CHECK-INSTR: cv.sra.sc.b a0, a1, a21393# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x48]1394# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1395 1396cv.sra.sc.b s0, s1, s21397# CHECK-INSTR: cv.sra.sc.b s0, s1, s21398# CHECK-ENCODING: [0x7b,0xd4,0x24,0x49]1399# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1400 1401//===----------------------------------------------------------------------===//1402// cv.sra.sci.h1403//===----------------------------------------------------------------------===//1404 1405cv.sra.sci.h t0, t1, 01406# CHECK-INSTR: cv.sra.sci.h t0, t1, 01407# CHECK-ENCODING: [0xfb,0x62,0x03,0x48]1408# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1409 1410cv.sra.sci.h t3, t4, 01411# CHECK-INSTR: cv.sra.sci.h t3, t4, 01412# CHECK-ENCODING: [0x7b,0xee,0x0e,0x48]1413# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1414 1415cv.sra.sci.h a0, a1, 71416# CHECK-INSTR: cv.sra.sci.h a0, a1, 71417# CHECK-ENCODING: [0x7b,0xe5,0x35,0x4a]1418# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1419 1420cv.sra.sci.h s0, s1, 151421# CHECK-INSTR: cv.sra.sci.h s0, s1, 151422# CHECK-ENCODING: [0x7b,0xe4,0x74,0x4a]1423# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1424 1425//===----------------------------------------------------------------------===//1426// cv.sra.sci.b1427//===----------------------------------------------------------------------===//1428 1429cv.sra.sci.b t0, t1, 01430# CHECK-INSTR: cv.sra.sci.b t0, t1, 01431# CHECK-ENCODING: [0xfb,0x72,0x03,0x48]1432# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1433 1434cv.sra.sci.b t3, t4, 01435# CHECK-INSTR: cv.sra.sci.b t3, t4, 01436# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x48]1437# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1438 1439cv.sra.sci.b a0, a1, 71440# CHECK-INSTR: cv.sra.sci.b a0, a1, 71441# CHECK-ENCODING: [0x7b,0xf5,0x35,0x4a]1442# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1443 1444cv.sra.sci.b s0, s1, 71445# CHECK-INSTR: cv.sra.sci.b s0, s1, 71446# CHECK-ENCODING: [0x7b,0xf4,0x34,0x4a]1447# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1448 1449//===----------------------------------------------------------------------===//1450// cv.sll.h1451//===----------------------------------------------------------------------===//1452 1453cv.sll.h t0, t1, t21454# CHECK-INSTR: cv.sll.h t0, t1, t21455# CHECK-ENCODING: [0xfb,0x02,0x73,0x50]1456# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1457 1458cv.sll.h t3, t4, t51459# CHECK-INSTR: cv.sll.h t3, t4, t51460# CHECK-ENCODING: [0x7b,0x8e,0xee,0x51]1461# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1462 1463cv.sll.h a0, a1, a21464# CHECK-INSTR: cv.sll.h a0, a1, a21465# CHECK-ENCODING: [0x7b,0x85,0xc5,0x50]1466# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1467 1468cv.sll.h s0, s1, s21469# CHECK-INSTR: cv.sll.h s0, s1, s21470# CHECK-ENCODING: [0x7b,0x84,0x24,0x51]1471# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1472 1473//===----------------------------------------------------------------------===//1474// cv.sll.b1475//===----------------------------------------------------------------------===//1476 1477cv.sll.b t0, t1, t21478# CHECK-INSTR: cv.sll.b t0, t1, t21479# CHECK-ENCODING: [0xfb,0x12,0x73,0x50]1480# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1481 1482cv.sll.b t3, t4, t51483# CHECK-INSTR: cv.sll.b t3, t4, t51484# CHECK-ENCODING: [0x7b,0x9e,0xee,0x51]1485# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1486 1487cv.sll.b a0, a1, a21488# CHECK-INSTR: cv.sll.b a0, a1, a21489# CHECK-ENCODING: [0x7b,0x95,0xc5,0x50]1490# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1491 1492cv.sll.b s0, s1, s21493# CHECK-INSTR: cv.sll.b s0, s1, s21494# CHECK-ENCODING: [0x7b,0x94,0x24,0x51]1495# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1496 1497//===----------------------------------------------------------------------===//1498// cv.sll.sc.h1499//===----------------------------------------------------------------------===//1500 1501cv.sll.sc.h t0, t1, t21502# CHECK-INSTR: cv.sll.sc.h t0, t1, t21503# CHECK-ENCODING: [0xfb,0x42,0x73,0x50]1504# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1505 1506cv.sll.sc.h t3, t4, t51507# CHECK-INSTR: cv.sll.sc.h t3, t4, t51508# CHECK-ENCODING: [0x7b,0xce,0xee,0x51]1509# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1510 1511cv.sll.sc.h a0, a1, a21512# CHECK-INSTR: cv.sll.sc.h a0, a1, a21513# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x50]1514# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1515 1516cv.sll.sc.h s0, s1, s21517# CHECK-INSTR: cv.sll.sc.h s0, s1, s21518# CHECK-ENCODING: [0x7b,0xc4,0x24,0x51]1519# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1520 1521//===----------------------------------------------------------------------===//1522// cv.sll.sc.b1523//===----------------------------------------------------------------------===//1524 1525cv.sll.sc.b t0, t1, t21526# CHECK-INSTR: cv.sll.sc.b t0, t1, t21527# CHECK-ENCODING: [0xfb,0x52,0x73,0x50]1528# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1529 1530cv.sll.sc.b t3, t4, t51531# CHECK-INSTR: cv.sll.sc.b t3, t4, t51532# CHECK-ENCODING: [0x7b,0xde,0xee,0x51]1533# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1534 1535cv.sll.sc.b a0, a1, a21536# CHECK-INSTR: cv.sll.sc.b a0, a1, a21537# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x50]1538# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1539 1540cv.sll.sc.b s0, s1, s21541# CHECK-INSTR: cv.sll.sc.b s0, s1, s21542# CHECK-ENCODING: [0x7b,0xd4,0x24,0x51]1543# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1544 1545//===----------------------------------------------------------------------===//1546// cv.sll.sci.h1547//===----------------------------------------------------------------------===//1548 1549cv.sll.sci.h t0, t1, 01550# CHECK-INSTR: cv.sll.sci.h t0, t1, 01551# CHECK-ENCODING: [0xfb,0x62,0x03,0x50]1552# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1553 1554cv.sll.sci.h t3, t4, 01555# CHECK-INSTR: cv.sll.sci.h t3, t4, 01556# CHECK-ENCODING: [0x7b,0xee,0x0e,0x50]1557# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1558 1559cv.sll.sci.h a0, a1, 71560# CHECK-INSTR: cv.sll.sci.h a0, a1, 71561# CHECK-ENCODING: [0x7b,0xe5,0x35,0x52]1562# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1563 1564cv.sll.sci.h s0, s1, 151565# CHECK-INSTR: cv.sll.sci.h s0, s1, 151566# CHECK-ENCODING: [0x7b,0xe4,0x74,0x52]1567# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1568 1569//===----------------------------------------------------------------------===//1570// cv.sll.sci.b1571//===----------------------------------------------------------------------===//1572 1573cv.sll.sci.b t0, t1, 01574# CHECK-INSTR: cv.sll.sci.b t0, t1, 01575# CHECK-ENCODING: [0xfb,0x72,0x03,0x50]1576# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1577 1578cv.sll.sci.b t3, t4, 01579# CHECK-INSTR: cv.sll.sci.b t3, t4, 01580# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x50]1581# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1582 1583cv.sll.sci.b a0, a1, 71584# CHECK-INSTR: cv.sll.sci.b a0, a1, 71585# CHECK-ENCODING: [0x7b,0xf5,0x35,0x52]1586# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1587 1588cv.sll.sci.b s0, s1, 71589# CHECK-INSTR: cv.sll.sci.b s0, s1, 71590# CHECK-ENCODING: [0x7b,0xf4,0x34,0x52]1591# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1592 1593//===----------------------------------------------------------------------===//1594// cv.or.h1595//===----------------------------------------------------------------------===//1596 1597cv.or.h t0, t1, t21598# CHECK-INSTR: cv.or.h t0, t1, t21599# CHECK-ENCODING: [0xfb,0x02,0x73,0x58]1600# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1601 1602cv.or.h t3, t4, t51603# CHECK-INSTR: cv.or.h t3, t4, t51604# CHECK-ENCODING: [0x7b,0x8e,0xee,0x59]1605# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1606 1607cv.or.h a0, a1, a21608# CHECK-INSTR: cv.or.h a0, a1, a21609# CHECK-ENCODING: [0x7b,0x85,0xc5,0x58]1610# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1611 1612cv.or.h s0, s1, s21613# CHECK-INSTR: cv.or.h s0, s1, s21614# CHECK-ENCODING: [0x7b,0x84,0x24,0x59]1615# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1616 1617//===----------------------------------------------------------------------===//1618// cv.or.b1619//===----------------------------------------------------------------------===//1620 1621cv.or.b t0, t1, t21622# CHECK-INSTR: cv.or.b t0, t1, t21623# CHECK-ENCODING: [0xfb,0x12,0x73,0x58]1624# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1625 1626cv.or.b t3, t4, t51627# CHECK-INSTR: cv.or.b t3, t4, t51628# CHECK-ENCODING: [0x7b,0x9e,0xee,0x59]1629# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1630 1631cv.or.b a0, a1, a21632# CHECK-INSTR: cv.or.b a0, a1, a21633# CHECK-ENCODING: [0x7b,0x95,0xc5,0x58]1634# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1635 1636cv.or.b s0, s1, s21637# CHECK-INSTR: cv.or.b s0, s1, s21638# CHECK-ENCODING: [0x7b,0x94,0x24,0x59]1639# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1640 1641//===----------------------------------------------------------------------===//1642// cv.or.sc.h1643//===----------------------------------------------------------------------===//1644 1645cv.or.sc.h t0, t1, t21646# CHECK-INSTR: cv.or.sc.h t0, t1, t21647# CHECK-ENCODING: [0xfb,0x42,0x73,0x58]1648# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1649 1650cv.or.sc.h t3, t4, t51651# CHECK-INSTR: cv.or.sc.h t3, t4, t51652# CHECK-ENCODING: [0x7b,0xce,0xee,0x59]1653# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1654 1655cv.or.sc.h a0, a1, a21656# CHECK-INSTR: cv.or.sc.h a0, a1, a21657# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x58]1658# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1659 1660cv.or.sc.h s0, s1, s21661# CHECK-INSTR: cv.or.sc.h s0, s1, s21662# CHECK-ENCODING: [0x7b,0xc4,0x24,0x59]1663# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1664 1665//===----------------------------------------------------------------------===//1666// cv.or.sc.b1667//===----------------------------------------------------------------------===//1668 1669cv.or.sc.b t0, t1, t21670# CHECK-INSTR: cv.or.sc.b t0, t1, t21671# CHECK-ENCODING: [0xfb,0x52,0x73,0x58]1672# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1673 1674cv.or.sc.b t3, t4, t51675# CHECK-INSTR: cv.or.sc.b t3, t4, t51676# CHECK-ENCODING: [0x7b,0xde,0xee,0x59]1677# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1678 1679cv.or.sc.b a0, a1, a21680# CHECK-INSTR: cv.or.sc.b a0, a1, a21681# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x58]1682# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1683 1684cv.or.sc.b s0, s1, s21685# CHECK-INSTR: cv.or.sc.b s0, s1, s21686# CHECK-ENCODING: [0x7b,0xd4,0x24,0x59]1687# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1688 1689//===----------------------------------------------------------------------===//1690// cv.or.sci.h1691//===----------------------------------------------------------------------===//1692 1693cv.or.sci.h t0, t1, 01694# CHECK-INSTR: cv.or.sci.h t0, t1, 01695# CHECK-ENCODING: [0xfb,0x62,0x03,0x58]1696# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1697 1698cv.or.sci.h t3, t4, -321699# CHECK-INSTR: cv.or.sci.h t3, t4, -321700# CHECK-ENCODING: [0x7b,0xee,0x0e,0x59]1701# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1702 1703cv.or.sci.h a0, a1, 71704# CHECK-INSTR: cv.or.sci.h a0, a1, 71705# CHECK-ENCODING: [0x7b,0xe5,0x35,0x5a]1706# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1707 1708cv.or.sci.h s0, s1, -11709# CHECK-INSTR: cv.or.sci.h s0, s1, -11710# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x5b]1711# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1712 1713//===----------------------------------------------------------------------===//1714// cv.or.sci.b1715//===----------------------------------------------------------------------===//1716 1717cv.or.sci.b t0, t1, 01718# CHECK-INSTR: cv.or.sci.b t0, t1, 01719# CHECK-ENCODING: [0xfb,0x72,0x03,0x58]1720# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1721 1722cv.or.sci.b t3, t4, -321723# CHECK-INSTR: cv.or.sci.b t3, t4, -321724# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x59]1725# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1726 1727cv.or.sci.b a0, a1, 71728# CHECK-INSTR: cv.or.sci.b a0, a1, 71729# CHECK-ENCODING: [0x7b,0xf5,0x35,0x5a]1730# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1731 1732cv.or.sci.b s0, s1, -11733# CHECK-INSTR: cv.or.sci.b s0, s1, -11734# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x5b]1735# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1736 1737//===----------------------------------------------------------------------===//1738// cv.xor.h1739//===----------------------------------------------------------------------===//1740 1741cv.xor.h t0, t1, t21742# CHECK-INSTR: cv.xor.h t0, t1, t21743# CHECK-ENCODING: [0xfb,0x02,0x73,0x60]1744# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1745 1746cv.xor.h t3, t4, t51747# CHECK-INSTR: cv.xor.h t3, t4, t51748# CHECK-ENCODING: [0x7b,0x8e,0xee,0x61]1749# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1750 1751cv.xor.h a0, a1, a21752# CHECK-INSTR: cv.xor.h a0, a1, a21753# CHECK-ENCODING: [0x7b,0x85,0xc5,0x60]1754# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1755 1756cv.xor.h s0, s1, s21757# CHECK-INSTR: cv.xor.h s0, s1, s21758# CHECK-ENCODING: [0x7b,0x84,0x24,0x61]1759# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1760 1761//===----------------------------------------------------------------------===//1762// cv.xor.b1763//===----------------------------------------------------------------------===//1764 1765cv.xor.b t0, t1, t21766# CHECK-INSTR: cv.xor.b t0, t1, t21767# CHECK-ENCODING: [0xfb,0x12,0x73,0x60]1768# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1769 1770cv.xor.b t3, t4, t51771# CHECK-INSTR: cv.xor.b t3, t4, t51772# CHECK-ENCODING: [0x7b,0x9e,0xee,0x61]1773# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1774 1775cv.xor.b a0, a1, a21776# CHECK-INSTR: cv.xor.b a0, a1, a21777# CHECK-ENCODING: [0x7b,0x95,0xc5,0x60]1778# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1779 1780cv.xor.b s0, s1, s21781# CHECK-INSTR: cv.xor.b s0, s1, s21782# CHECK-ENCODING: [0x7b,0x94,0x24,0x61]1783# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1784 1785//===----------------------------------------------------------------------===//1786// cv.xor.sc.h1787//===----------------------------------------------------------------------===//1788 1789cv.xor.sc.h t0, t1, t21790# CHECK-INSTR: cv.xor.sc.h t0, t1, t21791# CHECK-ENCODING: [0xfb,0x42,0x73,0x60]1792# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1793 1794cv.xor.sc.h t3, t4, t51795# CHECK-INSTR: cv.xor.sc.h t3, t4, t51796# CHECK-ENCODING: [0x7b,0xce,0xee,0x61]1797# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1798 1799cv.xor.sc.h a0, a1, a21800# CHECK-INSTR: cv.xor.sc.h a0, a1, a21801# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x60]1802# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1803 1804cv.xor.sc.h s0, s1, s21805# CHECK-INSTR: cv.xor.sc.h s0, s1, s21806# CHECK-ENCODING: [0x7b,0xc4,0x24,0x61]1807# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1808 1809//===----------------------------------------------------------------------===//1810// cv.xor.sc.b1811//===----------------------------------------------------------------------===//1812 1813cv.xor.sc.b t0, t1, t21814# CHECK-INSTR: cv.xor.sc.b t0, t1, t21815# CHECK-ENCODING: [0xfb,0x52,0x73,0x60]1816# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1817 1818cv.xor.sc.b t3, t4, t51819# CHECK-INSTR: cv.xor.sc.b t3, t4, t51820# CHECK-ENCODING: [0x7b,0xde,0xee,0x61]1821# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1822 1823cv.xor.sc.b a0, a1, a21824# CHECK-INSTR: cv.xor.sc.b a0, a1, a21825# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x60]1826# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1827 1828cv.xor.sc.b s0, s1, s21829# CHECK-INSTR: cv.xor.sc.b s0, s1, s21830# CHECK-ENCODING: [0x7b,0xd4,0x24,0x61]1831# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1832 1833//===----------------------------------------------------------------------===//1834// cv.xor.sci.h1835//===----------------------------------------------------------------------===//1836 1837cv.xor.sci.h t0, t1, 01838# CHECK-INSTR: cv.xor.sci.h t0, t1, 01839# CHECK-ENCODING: [0xfb,0x62,0x03,0x60]1840# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1841 1842cv.xor.sci.h t3, t4, -321843# CHECK-INSTR: cv.xor.sci.h t3, t4, -321844# CHECK-ENCODING: [0x7b,0xee,0x0e,0x61]1845# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1846 1847cv.xor.sci.h a0, a1, 71848# CHECK-INSTR: cv.xor.sci.h a0, a1, 71849# CHECK-ENCODING: [0x7b,0xe5,0x35,0x62]1850# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1851 1852cv.xor.sci.h s0, s1, -11853# CHECK-INSTR: cv.xor.sci.h s0, s1, -11854# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x63]1855# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1856 1857//===----------------------------------------------------------------------===//1858// cv.xor.sci.b1859//===----------------------------------------------------------------------===//1860 1861cv.xor.sci.b t0, t1, 01862# CHECK-INSTR: cv.xor.sci.b t0, t1, 01863# CHECK-ENCODING: [0xfb,0x72,0x03,0x60]1864# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1865 1866cv.xor.sci.b t3, t4, -321867# CHECK-INSTR: cv.xor.sci.b t3, t4, -321868# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x61]1869# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1870 1871cv.xor.sci.b a0, a1, 71872# CHECK-INSTR: cv.xor.sci.b a0, a1, 71873# CHECK-ENCODING: [0x7b,0xf5,0x35,0x62]1874# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1875 1876cv.xor.sci.b s0, s1, -11877# CHECK-INSTR: cv.xor.sci.b s0, s1, -11878# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x63]1879# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1880 1881//===----------------------------------------------------------------------===//1882// cv.and.h1883//===----------------------------------------------------------------------===//1884 1885cv.and.h t0, t1, t21886# CHECK-INSTR: cv.and.h t0, t1, t21887# CHECK-ENCODING: [0xfb,0x02,0x73,0x68]1888# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1889 1890cv.and.h t3, t4, t51891# CHECK-INSTR: cv.and.h t3, t4, t51892# CHECK-ENCODING: [0x7b,0x8e,0xee,0x69]1893# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1894 1895cv.and.h a0, a1, a21896# CHECK-INSTR: cv.and.h a0, a1, a21897# CHECK-ENCODING: [0x7b,0x85,0xc5,0x68]1898# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1899 1900cv.and.h s0, s1, s21901# CHECK-INSTR: cv.and.h s0, s1, s21902# CHECK-ENCODING: [0x7b,0x84,0x24,0x69]1903# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1904 1905//===----------------------------------------------------------------------===//1906// cv.and.b1907//===----------------------------------------------------------------------===//1908 1909cv.and.b t0, t1, t21910# CHECK-INSTR: cv.and.b t0, t1, t21911# CHECK-ENCODING: [0xfb,0x12,0x73,0x68]1912# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1913 1914cv.and.b t3, t4, t51915# CHECK-INSTR: cv.and.b t3, t4, t51916# CHECK-ENCODING: [0x7b,0x9e,0xee,0x69]1917# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1918 1919cv.and.b a0, a1, a21920# CHECK-INSTR: cv.and.b a0, a1, a21921# CHECK-ENCODING: [0x7b,0x95,0xc5,0x68]1922# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1923 1924cv.and.b s0, s1, s21925# CHECK-INSTR: cv.and.b s0, s1, s21926# CHECK-ENCODING: [0x7b,0x94,0x24,0x69]1927# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1928 1929//===----------------------------------------------------------------------===//1930// cv.and.sc.h1931//===----------------------------------------------------------------------===//1932 1933cv.and.sc.h t0, t1, t21934# CHECK-INSTR: cv.and.sc.h t0, t1, t21935# CHECK-ENCODING: [0xfb,0x42,0x73,0x68]1936# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1937 1938cv.and.sc.h t3, t4, t51939# CHECK-INSTR: cv.and.sc.h t3, t4, t51940# CHECK-ENCODING: [0x7b,0xce,0xee,0x69]1941# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1942 1943cv.and.sc.h a0, a1, a21944# CHECK-INSTR: cv.and.sc.h a0, a1, a21945# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x68]1946# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1947 1948cv.and.sc.h s0, s1, s21949# CHECK-INSTR: cv.and.sc.h s0, s1, s21950# CHECK-ENCODING: [0x7b,0xc4,0x24,0x69]1951# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1952 1953//===----------------------------------------------------------------------===//1954// cv.and.sc.b1955//===----------------------------------------------------------------------===//1956 1957cv.and.sc.b t0, t1, t21958# CHECK-INSTR: cv.and.sc.b t0, t1, t21959# CHECK-ENCODING: [0xfb,0x52,0x73,0x68]1960# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1961 1962cv.and.sc.b t3, t4, t51963# CHECK-INSTR: cv.and.sc.b t3, t4, t51964# CHECK-ENCODING: [0x7b,0xde,0xee,0x69]1965# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1966 1967cv.and.sc.b a0, a1, a21968# CHECK-INSTR: cv.and.sc.b a0, a1, a21969# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x68]1970# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1971 1972cv.and.sc.b s0, s1, s21973# CHECK-INSTR: cv.and.sc.b s0, s1, s21974# CHECK-ENCODING: [0x7b,0xd4,0x24,0x69]1975# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1976 1977//===----------------------------------------------------------------------===//1978// cv.and.sci.h1979//===----------------------------------------------------------------------===//1980 1981cv.and.sci.h t0, t1, 01982# CHECK-INSTR: cv.and.sci.h t0, t1, 01983# CHECK-ENCODING: [0xfb,0x62,0x03,0x68]1984# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1985 1986cv.and.sci.h t3, t4, -321987# CHECK-INSTR: cv.and.sci.h t3, t4, -321988# CHECK-ENCODING: [0x7b,0xee,0x0e,0x69]1989# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1990 1991cv.and.sci.h a0, a1, 71992# CHECK-INSTR: cv.and.sci.h a0, a1, 71993# CHECK-ENCODING: [0x7b,0xe5,0x35,0x6a]1994# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}1995 1996cv.and.sci.h s0, s1, -11997# CHECK-INSTR: cv.and.sci.h s0, s1, -11998# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x6b]1999# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2000 2001//===----------------------------------------------------------------------===//2002// cv.and.sci.b2003//===----------------------------------------------------------------------===//2004 2005cv.and.sci.b t0, t1, 02006# CHECK-INSTR: cv.and.sci.b t0, t1, 02007# CHECK-ENCODING: [0xfb,0x72,0x03,0x68]2008# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2009 2010cv.and.sci.b t3, t4, -322011# CHECK-INSTR: cv.and.sci.b t3, t4, -322012# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x69]2013# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2014 2015cv.and.sci.b a0, a1, 72016# CHECK-INSTR: cv.and.sci.b a0, a1, 72017# CHECK-ENCODING: [0x7b,0xf5,0x35,0x6a]2018# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2019 2020cv.and.sci.b s0, s1, -12021# CHECK-INSTR: cv.and.sci.b s0, s1, -12022# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x6b]2023# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2024 2025//===----------------------------------------------------------------------===//2026// cv.abs.h2027//===----------------------------------------------------------------------===//2028 2029cv.abs.h t0, t12030# CHECK-INSTR: cv.abs.h t0, t12031# CHECK-ENCODING: [0xfb,0x02,0x03,0x70]2032# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2033 2034cv.abs.h t3, t42035# CHECK-INSTR: cv.abs.h t3, t42036# CHECK-ENCODING: [0x7b,0x8e,0x0e,0x70]2037# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2038 2039cv.abs.h a0, a12040# CHECK-INSTR: cv.abs.h a0, a12041# CHECK-ENCODING: [0x7b,0x85,0x05,0x70]2042# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2043 2044cv.abs.h s0, s12045# CHECK-INSTR: cv.abs.h s0, s12046# CHECK-ENCODING: [0x7b,0x84,0x04,0x70]2047# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2048 2049//===----------------------------------------------------------------------===//2050// cv.abs.b2051//===----------------------------------------------------------------------===//2052 2053cv.abs.b t0, t12054# CHECK-INSTR: cv.abs.b t0, t12055# CHECK-ENCODING: [0xfb,0x12,0x03,0x70]2056# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2057 2058cv.abs.b t3, t42059# CHECK-INSTR: cv.abs.b t3, t42060# CHECK-ENCODING: [0x7b,0x9e,0x0e,0x70]2061# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2062 2063cv.abs.b a0, a12064# CHECK-INSTR: cv.abs.b a0, a12065# CHECK-ENCODING: [0x7b,0x95,0x05,0x70]2066# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2067 2068cv.abs.b s0, s12069# CHECK-INSTR: cv.abs.b s0, s12070# CHECK-ENCODING: [0x7b,0x94,0x04,0x70]2071# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2072 2073//===----------------------------------------------------------------------===//2074// cv.dotup.h2075//===----------------------------------------------------------------------===//2076 2077cv.dotup.h t0, t1, t22078# CHECK-INSTR: cv.dotup.h t0, t1, t22079# CHECK-ENCODING: [0xfb,0x02,0x73,0x80]2080# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2081 2082cv.dotup.h t3, t4, t52083# CHECK-INSTR: cv.dotup.h t3, t4, t52084# CHECK-ENCODING: [0x7b,0x8e,0xee,0x81]2085# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2086 2087cv.dotup.h a0, a1, a22088# CHECK-INSTR: cv.dotup.h a0, a1, a22089# CHECK-ENCODING: [0x7b,0x85,0xc5,0x80]2090# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2091 2092cv.dotup.h s0, s1, s22093# CHECK-INSTR: cv.dotup.h s0, s1, s22094# CHECK-ENCODING: [0x7b,0x84,0x24,0x81]2095# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2096 2097//===----------------------------------------------------------------------===//2098// cv.dotup.b2099//===----------------------------------------------------------------------===//2100 2101cv.dotup.b t0, t1, t22102# CHECK-INSTR: cv.dotup.b t0, t1, t22103# CHECK-ENCODING: [0xfb,0x12,0x73,0x80]2104# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2105 2106cv.dotup.b t3, t4, t52107# CHECK-INSTR: cv.dotup.b t3, t4, t52108# CHECK-ENCODING: [0x7b,0x9e,0xee,0x81]2109# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2110 2111cv.dotup.b a0, a1, a22112# CHECK-INSTR: cv.dotup.b a0, a1, a22113# CHECK-ENCODING: [0x7b,0x95,0xc5,0x80]2114# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2115 2116cv.dotup.b s0, s1, s22117# CHECK-INSTR: cv.dotup.b s0, s1, s22118# CHECK-ENCODING: [0x7b,0x94,0x24,0x81]2119# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2120 2121//===----------------------------------------------------------------------===//2122// cv.dotup.sc.h2123//===----------------------------------------------------------------------===//2124 2125cv.dotup.sc.h t0, t1, t22126# CHECK-INSTR: cv.dotup.sc.h t0, t1, t22127# CHECK-ENCODING: [0xfb,0x42,0x73,0x80]2128# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2129 2130cv.dotup.sc.h t3, t4, t52131# CHECK-INSTR: cv.dotup.sc.h t3, t4, t52132# CHECK-ENCODING: [0x7b,0xce,0xee,0x81]2133# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2134 2135cv.dotup.sc.h a0, a1, a22136# CHECK-INSTR: cv.dotup.sc.h a0, a1, a22137# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x80]2138# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2139 2140cv.dotup.sc.h s0, s1, s22141# CHECK-INSTR: cv.dotup.sc.h s0, s1, s22142# CHECK-ENCODING: [0x7b,0xc4,0x24,0x81]2143# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2144 2145//===----------------------------------------------------------------------===//2146// cv.dotup.sc.b2147//===----------------------------------------------------------------------===//2148 2149cv.dotup.sc.b t0, t1, t22150# CHECK-INSTR: cv.dotup.sc.b t0, t1, t22151# CHECK-ENCODING: [0xfb,0x52,0x73,0x80]2152# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2153 2154cv.dotup.sc.b t3, t4, t52155# CHECK-INSTR: cv.dotup.sc.b t3, t4, t52156# CHECK-ENCODING: [0x7b,0xde,0xee,0x81]2157# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2158 2159cv.dotup.sc.b a0, a1, a22160# CHECK-INSTR: cv.dotup.sc.b a0, a1, a22161# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x80]2162# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2163 2164cv.dotup.sc.b s0, s1, s22165# CHECK-INSTR: cv.dotup.sc.b s0, s1, s22166# CHECK-ENCODING: [0x7b,0xd4,0x24,0x81]2167# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2168 2169//===----------------------------------------------------------------------===//2170// cv.dotup.sci.h2171//===----------------------------------------------------------------------===//2172 2173cv.dotup.sci.h t0, t1, 02174# CHECK-INSTR: cv.dotup.sci.h t0, t1, 02175# CHECK-ENCODING: [0xfb,0x62,0x03,0x80]2176# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2177 2178cv.dotup.sci.h t3, t4, 322179# CHECK-INSTR: cv.dotup.sci.h t3, t4, 322180# CHECK-ENCODING: [0x7b,0xee,0x0e,0x81]2181# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2182 2183cv.dotup.sci.h a0, a1, 72184# CHECK-INSTR: cv.dotup.sci.h a0, a1, 72185# CHECK-ENCODING: [0x7b,0xe5,0x35,0x82]2186# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2187 2188cv.dotup.sci.h s0, s1, 632189# CHECK-INSTR: cv.dotup.sci.h s0, s1, 632190# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x83]2191# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2192 2193//===----------------------------------------------------------------------===//2194// cv.dotup.sci.b2195//===----------------------------------------------------------------------===//2196 2197cv.dotup.sci.b t0, t1, 02198# CHECK-INSTR: cv.dotup.sci.b t0, t1, 02199# CHECK-ENCODING: [0xfb,0x72,0x03,0x80]2200# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2201 2202cv.dotup.sci.b t3, t4, 322203# CHECK-INSTR: cv.dotup.sci.b t3, t4, 322204# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x81]2205# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2206 2207cv.dotup.sci.b a0, a1, 72208# CHECK-INSTR: cv.dotup.sci.b a0, a1, 72209# CHECK-ENCODING: [0x7b,0xf5,0x35,0x82]2210# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2211 2212cv.dotup.sci.b s0, s1, 632213# CHECK-INSTR: cv.dotup.sci.b s0, s1, 632214# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x83]2215# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2216 2217//===----------------------------------------------------------------------===//2218// cv.dotusp.h2219//===----------------------------------------------------------------------===//2220 2221cv.dotusp.h t0, t1, t22222# CHECK-INSTR: cv.dotusp.h t0, t1, t22223# CHECK-ENCODING: [0xfb,0x02,0x73,0x88]2224# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2225 2226cv.dotusp.h t3, t4, t52227# CHECK-INSTR: cv.dotusp.h t3, t4, t52228# CHECK-ENCODING: [0x7b,0x8e,0xee,0x89]2229# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2230 2231cv.dotusp.h a0, a1, a22232# CHECK-INSTR: cv.dotusp.h a0, a1, a22233# CHECK-ENCODING: [0x7b,0x85,0xc5,0x88]2234# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2235 2236cv.dotusp.h s0, s1, s22237# CHECK-INSTR: cv.dotusp.h s0, s1, s22238# CHECK-ENCODING: [0x7b,0x84,0x24,0x89]2239# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2240 2241//===----------------------------------------------------------------------===//2242// cv.dotusp.b2243//===----------------------------------------------------------------------===//2244 2245cv.dotusp.b t0, t1, t22246# CHECK-INSTR: cv.dotusp.b t0, t1, t22247# CHECK-ENCODING: [0xfb,0x12,0x73,0x88]2248# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2249 2250cv.dotusp.b t3, t4, t52251# CHECK-INSTR: cv.dotusp.b t3, t4, t52252# CHECK-ENCODING: [0x7b,0x9e,0xee,0x89]2253# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2254 2255cv.dotusp.b a0, a1, a22256# CHECK-INSTR: cv.dotusp.b a0, a1, a22257# CHECK-ENCODING: [0x7b,0x95,0xc5,0x88]2258# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2259 2260cv.dotusp.b s0, s1, s22261# CHECK-INSTR: cv.dotusp.b s0, s1, s22262# CHECK-ENCODING: [0x7b,0x94,0x24,0x89]2263# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2264 2265//===----------------------------------------------------------------------===//2266// cv.dotusp.sc.h2267//===----------------------------------------------------------------------===//2268 2269cv.dotusp.sc.h t0, t1, t22270# CHECK-INSTR: cv.dotusp.sc.h t0, t1, t22271# CHECK-ENCODING: [0xfb,0x42,0x73,0x88]2272# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2273 2274cv.dotusp.sc.h t3, t4, t52275# CHECK-INSTR: cv.dotusp.sc.h t3, t4, t52276# CHECK-ENCODING: [0x7b,0xce,0xee,0x89]2277# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2278 2279cv.dotusp.sc.h a0, a1, a22280# CHECK-INSTR: cv.dotusp.sc.h a0, a1, a22281# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x88]2282# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2283 2284cv.dotusp.sc.h s0, s1, s22285# CHECK-INSTR: cv.dotusp.sc.h s0, s1, s22286# CHECK-ENCODING: [0x7b,0xc4,0x24,0x89]2287# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2288 2289//===----------------------------------------------------------------------===//2290// cv.dotusp.sc.b2291//===----------------------------------------------------------------------===//2292 2293cv.dotusp.sc.b t0, t1, t22294# CHECK-INSTR: cv.dotusp.sc.b t0, t1, t22295# CHECK-ENCODING: [0xfb,0x52,0x73,0x88]2296# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2297 2298cv.dotusp.sc.b t3, t4, t52299# CHECK-INSTR: cv.dotusp.sc.b t3, t4, t52300# CHECK-ENCODING: [0x7b,0xde,0xee,0x89]2301# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2302 2303cv.dotusp.sc.b a0, a1, a22304# CHECK-INSTR: cv.dotusp.sc.b a0, a1, a22305# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x88]2306# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2307 2308cv.dotusp.sc.b s0, s1, s22309# CHECK-INSTR: cv.dotusp.sc.b s0, s1, s22310# CHECK-ENCODING: [0x7b,0xd4,0x24,0x89]2311# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2312 2313//===----------------------------------------------------------------------===//2314// cv.dotusp.sci.h2315//===----------------------------------------------------------------------===//2316 2317cv.dotusp.sci.h t0, t1, 02318# CHECK-INSTR: cv.dotusp.sci.h t0, t1, 02319# CHECK-ENCODING: [0xfb,0x62,0x03,0x88]2320# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2321 2322cv.dotusp.sci.h t3, t4, -322323# CHECK-INSTR: cv.dotusp.sci.h t3, t4, -322324# CHECK-ENCODING: [0x7b,0xee,0x0e,0x89]2325# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2326 2327cv.dotusp.sci.h a0, a1, 72328# CHECK-INSTR: cv.dotusp.sci.h a0, a1, 72329# CHECK-ENCODING: [0x7b,0xe5,0x35,0x8a]2330# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2331 2332cv.dotusp.sci.h s0, s1, -12333# CHECK-INSTR: cv.dotusp.sci.h s0, s1, -12334# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x8b]2335# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2336 2337//===----------------------------------------------------------------------===//2338// cv.dotusp.sci.b2339//===----------------------------------------------------------------------===//2340 2341cv.dotusp.sci.b t0, t1, 02342# CHECK-INSTR: cv.dotusp.sci.b t0, t1, 02343# CHECK-ENCODING: [0xfb,0x72,0x03,0x88]2344# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2345 2346cv.dotusp.sci.b t3, t4, -322347# CHECK-INSTR: cv.dotusp.sci.b t3, t4, -322348# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x89]2349# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2350 2351cv.dotusp.sci.b a0, a1, 72352# CHECK-INSTR: cv.dotusp.sci.b a0, a1, 72353# CHECK-ENCODING: [0x7b,0xf5,0x35,0x8a]2354# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2355 2356cv.dotusp.sci.b s0, s1, -12357# CHECK-INSTR: cv.dotusp.sci.b s0, s1, -12358# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x8b]2359# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2360 2361//===----------------------------------------------------------------------===//2362// cv.dotsp.h2363//===----------------------------------------------------------------------===//2364 2365cv.dotsp.h t0, t1, t22366# CHECK-INSTR: cv.dotsp.h t0, t1, t22367# CHECK-ENCODING: [0xfb,0x02,0x73,0x90]2368# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2369 2370cv.dotsp.h t3, t4, t52371# CHECK-INSTR: cv.dotsp.h t3, t4, t52372# CHECK-ENCODING: [0x7b,0x8e,0xee,0x91]2373# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2374 2375cv.dotsp.h a0, a1, a22376# CHECK-INSTR: cv.dotsp.h a0, a1, a22377# CHECK-ENCODING: [0x7b,0x85,0xc5,0x90]2378# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2379 2380cv.dotsp.h s0, s1, s22381# CHECK-INSTR: cv.dotsp.h s0, s1, s22382# CHECK-ENCODING: [0x7b,0x84,0x24,0x91]2383# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2384 2385//===----------------------------------------------------------------------===//2386// cv.dotsp.b2387//===----------------------------------------------------------------------===//2388 2389cv.dotsp.b t0, t1, t22390# CHECK-INSTR: cv.dotsp.b t0, t1, t22391# CHECK-ENCODING: [0xfb,0x12,0x73,0x90]2392# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2393 2394cv.dotsp.b t3, t4, t52395# CHECK-INSTR: cv.dotsp.b t3, t4, t52396# CHECK-ENCODING: [0x7b,0x9e,0xee,0x91]2397# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2398 2399cv.dotsp.b a0, a1, a22400# CHECK-INSTR: cv.dotsp.b a0, a1, a22401# CHECK-ENCODING: [0x7b,0x95,0xc5,0x90]2402# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2403 2404cv.dotsp.b s0, s1, s22405# CHECK-INSTR: cv.dotsp.b s0, s1, s22406# CHECK-ENCODING: [0x7b,0x94,0x24,0x91]2407# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2408 2409//===----------------------------------------------------------------------===//2410// cv.dotsp.sc.h2411//===----------------------------------------------------------------------===//2412 2413cv.dotsp.sc.h t0, t1, t22414# CHECK-INSTR: cv.dotsp.sc.h t0, t1, t22415# CHECK-ENCODING: [0xfb,0x42,0x73,0x90]2416# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2417 2418cv.dotsp.sc.h t3, t4, t52419# CHECK-INSTR: cv.dotsp.sc.h t3, t4, t52420# CHECK-ENCODING: [0x7b,0xce,0xee,0x91]2421# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2422 2423cv.dotsp.sc.h a0, a1, a22424# CHECK-INSTR: cv.dotsp.sc.h a0, a1, a22425# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x90]2426# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2427 2428cv.dotsp.sc.h s0, s1, s22429# CHECK-INSTR: cv.dotsp.sc.h s0, s1, s22430# CHECK-ENCODING: [0x7b,0xc4,0x24,0x91]2431# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2432 2433//===----------------------------------------------------------------------===//2434// cv.dotsp.sc.b2435//===----------------------------------------------------------------------===//2436 2437cv.dotsp.sc.b t0, t1, t22438# CHECK-INSTR: cv.dotsp.sc.b t0, t1, t22439# CHECK-ENCODING: [0xfb,0x52,0x73,0x90]2440# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2441 2442cv.dotsp.sc.b t3, t4, t52443# CHECK-INSTR: cv.dotsp.sc.b t3, t4, t52444# CHECK-ENCODING: [0x7b,0xde,0xee,0x91]2445# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2446 2447cv.dotsp.sc.b a0, a1, a22448# CHECK-INSTR: cv.dotsp.sc.b a0, a1, a22449# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x90]2450# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2451 2452cv.dotsp.sc.b s0, s1, s22453# CHECK-INSTR: cv.dotsp.sc.b s0, s1, s22454# CHECK-ENCODING: [0x7b,0xd4,0x24,0x91]2455# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2456 2457//===----------------------------------------------------------------------===//2458// cv.dotsp.sci.h2459//===----------------------------------------------------------------------===//2460 2461cv.dotsp.sci.h t0, t1, 02462# CHECK-INSTR: cv.dotsp.sci.h t0, t1, 02463# CHECK-ENCODING: [0xfb,0x62,0x03,0x90]2464# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2465 2466cv.dotsp.sci.h t3, t4, -322467# CHECK-INSTR: cv.dotsp.sci.h t3, t4, -322468# CHECK-ENCODING: [0x7b,0xee,0x0e,0x91]2469# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2470 2471cv.dotsp.sci.h a0, a1, 72472# CHECK-INSTR: cv.dotsp.sci.h a0, a1, 72473# CHECK-ENCODING: [0x7b,0xe5,0x35,0x92]2474# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2475 2476cv.dotsp.sci.h s0, s1, -12477# CHECK-INSTR: cv.dotsp.sci.h s0, s1, -12478# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x93]2479# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2480 2481//===----------------------------------------------------------------------===//2482// cv.dotsp.sci.b2483//===----------------------------------------------------------------------===//2484 2485cv.dotsp.sci.b t0, t1, 02486# CHECK-INSTR: cv.dotsp.sci.b t0, t1, 02487# CHECK-ENCODING: [0xfb,0x72,0x03,0x90]2488# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2489 2490cv.dotsp.sci.b t3, t4, -322491# CHECK-INSTR: cv.dotsp.sci.b t3, t4, -322492# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x91]2493# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2494 2495cv.dotsp.sci.b a0, a1, 72496# CHECK-INSTR: cv.dotsp.sci.b a0, a1, 72497# CHECK-ENCODING: [0x7b,0xf5,0x35,0x92]2498# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2499 2500cv.dotsp.sci.b s0, s1, -12501# CHECK-INSTR: cv.dotsp.sci.b s0, s1, -12502# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x93]2503# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2504 2505//===----------------------------------------------------------------------===//2506// cv.sdotup.h2507//===----------------------------------------------------------------------===//2508 2509cv.sdotup.h t0, t1, t22510# CHECK-INSTR: cv.sdotup.h t0, t1, t22511# CHECK-ENCODING: [0xfb,0x02,0x73,0x98]2512# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2513 2514cv.sdotup.h t3, t4, t52515# CHECK-INSTR: cv.sdotup.h t3, t4, t52516# CHECK-ENCODING: [0x7b,0x8e,0xee,0x99]2517# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2518 2519cv.sdotup.h a0, a1, a22520# CHECK-INSTR: cv.sdotup.h a0, a1, a22521# CHECK-ENCODING: [0x7b,0x85,0xc5,0x98]2522# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2523 2524cv.sdotup.h s0, s1, s22525# CHECK-INSTR: cv.sdotup.h s0, s1, s22526# CHECK-ENCODING: [0x7b,0x84,0x24,0x99]2527# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2528 2529//===----------------------------------------------------------------------===//2530// cv.sdotup.b2531//===----------------------------------------------------------------------===//2532 2533cv.sdotup.b t0, t1, t22534# CHECK-INSTR: cv.sdotup.b t0, t1, t22535# CHECK-ENCODING: [0xfb,0x12,0x73,0x98]2536# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2537 2538cv.sdotup.b t3, t4, t52539# CHECK-INSTR: cv.sdotup.b t3, t4, t52540# CHECK-ENCODING: [0x7b,0x9e,0xee,0x99]2541# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2542 2543cv.sdotup.b a0, a1, a22544# CHECK-INSTR: cv.sdotup.b a0, a1, a22545# CHECK-ENCODING: [0x7b,0x95,0xc5,0x98]2546# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2547 2548cv.sdotup.b s0, s1, s22549# CHECK-INSTR: cv.sdotup.b s0, s1, s22550# CHECK-ENCODING: [0x7b,0x94,0x24,0x99]2551# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2552 2553//===----------------------------------------------------------------------===//2554// cv.sdotup.sc.h2555//===----------------------------------------------------------------------===//2556 2557cv.sdotup.sc.h t0, t1, t22558# CHECK-INSTR: cv.sdotup.sc.h t0, t1, t22559# CHECK-ENCODING: [0xfb,0x42,0x73,0x98]2560# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2561 2562cv.sdotup.sc.h t3, t4, t52563# CHECK-INSTR: cv.sdotup.sc.h t3, t4, t52564# CHECK-ENCODING: [0x7b,0xce,0xee,0x99]2565# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2566 2567cv.sdotup.sc.h a0, a1, a22568# CHECK-INSTR: cv.sdotup.sc.h a0, a1, a22569# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x98]2570# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2571 2572cv.sdotup.sc.h s0, s1, s22573# CHECK-INSTR: cv.sdotup.sc.h s0, s1, s22574# CHECK-ENCODING: [0x7b,0xc4,0x24,0x99]2575# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2576 2577//===----------------------------------------------------------------------===//2578// cv.sdotup.sc.b2579//===----------------------------------------------------------------------===//2580 2581cv.sdotup.sc.b t0, t1, t22582# CHECK-INSTR: cv.sdotup.sc.b t0, t1, t22583# CHECK-ENCODING: [0xfb,0x52,0x73,0x98]2584# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2585 2586cv.sdotup.sc.b t3, t4, t52587# CHECK-INSTR: cv.sdotup.sc.b t3, t4, t52588# CHECK-ENCODING: [0x7b,0xde,0xee,0x99]2589# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2590 2591cv.sdotup.sc.b a0, a1, a22592# CHECK-INSTR: cv.sdotup.sc.b a0, a1, a22593# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x98]2594# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2595 2596cv.sdotup.sc.b s0, s1, s22597# CHECK-INSTR: cv.sdotup.sc.b s0, s1, s22598# CHECK-ENCODING: [0x7b,0xd4,0x24,0x99]2599# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2600 2601//===----------------------------------------------------------------------===//2602// cv.sdotup.sci.h2603//===----------------------------------------------------------------------===//2604 2605cv.sdotup.sci.h t0, t1, 02606# CHECK-INSTR: cv.sdotup.sci.h t0, t1, 02607# CHECK-ENCODING: [0xfb,0x62,0x03,0x98]2608# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2609 2610cv.sdotup.sci.h t3, t4, 322611# CHECK-INSTR: cv.sdotup.sci.h t3, t4, 322612# CHECK-ENCODING: [0x7b,0xee,0x0e,0x99]2613# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2614 2615cv.sdotup.sci.h a0, a1, 72616# CHECK-INSTR: cv.sdotup.sci.h a0, a1, 72617# CHECK-ENCODING: [0x7b,0xe5,0x35,0x9a]2618# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2619 2620cv.sdotup.sci.h s0, s1, 632621# CHECK-INSTR: cv.sdotup.sci.h s0, s1, 632622# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x9b]2623# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2624 2625//===----------------------------------------------------------------------===//2626// cv.sdotup.sci.b2627//===----------------------------------------------------------------------===//2628 2629cv.sdotup.sci.b t0, t1, 02630# CHECK-INSTR: cv.sdotup.sci.b t0, t1, 02631# CHECK-ENCODING: [0xfb,0x72,0x03,0x98]2632# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2633 2634cv.sdotup.sci.b t3, t4, 322635# CHECK-INSTR: cv.sdotup.sci.b t3, t4, 322636# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x99]2637# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2638 2639cv.sdotup.sci.b a0, a1, 72640# CHECK-INSTR: cv.sdotup.sci.b a0, a1, 72641# CHECK-ENCODING: [0x7b,0xf5,0x35,0x9a]2642# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2643 2644cv.sdotup.sci.b s0, s1, 632645# CHECK-INSTR: cv.sdotup.sci.b s0, s1, 632646# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x9b]2647# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2648 2649//===----------------------------------------------------------------------===//2650// cv.sdotusp.h2651//===----------------------------------------------------------------------===//2652 2653cv.sdotusp.h t0, t1, t22654# CHECK-INSTR: cv.sdotusp.h t0, t1, t22655# CHECK-ENCODING: [0xfb,0x02,0x73,0xa0]2656# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2657 2658cv.sdotusp.h t3, t4, t52659# CHECK-INSTR: cv.sdotusp.h t3, t4, t52660# CHECK-ENCODING: [0x7b,0x8e,0xee,0xa1]2661# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2662 2663cv.sdotusp.h a0, a1, a22664# CHECK-INSTR: cv.sdotusp.h a0, a1, a22665# CHECK-ENCODING: [0x7b,0x85,0xc5,0xa0]2666# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2667 2668cv.sdotusp.h s0, s1, s22669# CHECK-INSTR: cv.sdotusp.h s0, s1, s22670# CHECK-ENCODING: [0x7b,0x84,0x24,0xa1]2671# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2672 2673//===----------------------------------------------------------------------===//2674// cv.sdotusp.b2675//===----------------------------------------------------------------------===//2676 2677cv.sdotusp.b t0, t1, t22678# CHECK-INSTR: cv.sdotusp.b t0, t1, t22679# CHECK-ENCODING: [0xfb,0x12,0x73,0xa0]2680# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2681 2682cv.sdotusp.b t3, t4, t52683# CHECK-INSTR: cv.sdotusp.b t3, t4, t52684# CHECK-ENCODING: [0x7b,0x9e,0xee,0xa1]2685# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2686 2687cv.sdotusp.b a0, a1, a22688# CHECK-INSTR: cv.sdotusp.b a0, a1, a22689# CHECK-ENCODING: [0x7b,0x95,0xc5,0xa0]2690# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2691 2692cv.sdotusp.b s0, s1, s22693# CHECK-INSTR: cv.sdotusp.b s0, s1, s22694# CHECK-ENCODING: [0x7b,0x94,0x24,0xa1]2695# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2696 2697//===----------------------------------------------------------------------===//2698// cv.sdotusp.sc.h2699//===----------------------------------------------------------------------===//2700 2701cv.sdotusp.sc.h t0, t1, t22702# CHECK-INSTR: cv.sdotusp.sc.h t0, t1, t22703# CHECK-ENCODING: [0xfb,0x42,0x73,0xa0]2704# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2705 2706cv.sdotusp.sc.h t3, t4, t52707# CHECK-INSTR: cv.sdotusp.sc.h t3, t4, t52708# CHECK-ENCODING: [0x7b,0xce,0xee,0xa1]2709# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2710 2711cv.sdotusp.sc.h a0, a1, a22712# CHECK-INSTR: cv.sdotusp.sc.h a0, a1, a22713# CHECK-ENCODING: [0x7b,0xc5,0xc5,0xa0]2714# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2715 2716cv.sdotusp.sc.h s0, s1, s22717# CHECK-INSTR: cv.sdotusp.sc.h s0, s1, s22718# CHECK-ENCODING: [0x7b,0xc4,0x24,0xa1]2719# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2720 2721//===----------------------------------------------------------------------===//2722// cv.sdotusp.sc.b2723//===----------------------------------------------------------------------===//2724 2725cv.sdotusp.sc.b t0, t1, t22726# CHECK-INSTR: cv.sdotusp.sc.b t0, t1, t22727# CHECK-ENCODING: [0xfb,0x52,0x73,0xa0]2728# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2729 2730cv.sdotusp.sc.b t3, t4, t52731# CHECK-INSTR: cv.sdotusp.sc.b t3, t4, t52732# CHECK-ENCODING: [0x7b,0xde,0xee,0xa1]2733# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2734 2735cv.sdotusp.sc.b a0, a1, a22736# CHECK-INSTR: cv.sdotusp.sc.b a0, a1, a22737# CHECK-ENCODING: [0x7b,0xd5,0xc5,0xa0]2738# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2739 2740cv.sdotusp.sc.b s0, s1, s22741# CHECK-INSTR: cv.sdotusp.sc.b s0, s1, s22742# CHECK-ENCODING: [0x7b,0xd4,0x24,0xa1]2743# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2744 2745//===----------------------------------------------------------------------===//2746// cv.sdotusp.sci.h2747//===----------------------------------------------------------------------===//2748 2749cv.sdotusp.sci.h t0, t1, 02750# CHECK-INSTR: cv.sdotusp.sci.h t0, t1, 02751# CHECK-ENCODING: [0xfb,0x62,0x03,0xa0]2752# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2753 2754cv.sdotusp.sci.h t3, t4, -322755# CHECK-INSTR: cv.sdotusp.sci.h t3, t4, -322756# CHECK-ENCODING: [0x7b,0xee,0x0e,0xa1]2757# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2758 2759cv.sdotusp.sci.h a0, a1, 72760# CHECK-INSTR: cv.sdotusp.sci.h a0, a1, 72761# CHECK-ENCODING: [0x7b,0xe5,0x35,0xa2]2762# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2763 2764cv.sdotusp.sci.h s0, s1, -12765# CHECK-INSTR: cv.sdotusp.sci.h s0, s1, -12766# CHECK-ENCODING: [0x7b,0xe4,0xf4,0xa3]2767# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2768 2769//===----------------------------------------------------------------------===//2770// cv.sdotusp.sci.b2771//===----------------------------------------------------------------------===//2772 2773cv.sdotusp.sci.b t0, t1, 02774# CHECK-INSTR: cv.sdotusp.sci.b t0, t1, 02775# CHECK-ENCODING: [0xfb,0x72,0x03,0xa0]2776# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2777 2778cv.sdotusp.sci.b t3, t4, -322779# CHECK-INSTR: cv.sdotusp.sci.b t3, t4, -322780# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xa1]2781# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2782 2783cv.sdotusp.sci.b a0, a1, 72784# CHECK-INSTR: cv.sdotusp.sci.b a0, a1, 72785# CHECK-ENCODING: [0x7b,0xf5,0x35,0xa2]2786# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2787 2788cv.sdotusp.sci.b s0, s1, -12789# CHECK-INSTR: cv.sdotusp.sci.b s0, s1, -12790# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xa3]2791# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2792 2793//===----------------------------------------------------------------------===//2794// cv.sdotsp.h2795//===----------------------------------------------------------------------===//2796 2797cv.sdotsp.h t0, t1, t22798# CHECK-INSTR: cv.sdotsp.h t0, t1, t22799# CHECK-ENCODING: [0xfb,0x02,0x73,0xa8]2800# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2801 2802cv.sdotsp.h t3, t4, t52803# CHECK-INSTR: cv.sdotsp.h t3, t4, t52804# CHECK-ENCODING: [0x7b,0x8e,0xee,0xa9]2805# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2806 2807cv.sdotsp.h a0, a1, a22808# CHECK-INSTR: cv.sdotsp.h a0, a1, a22809# CHECK-ENCODING: [0x7b,0x85,0xc5,0xa8]2810# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2811 2812cv.sdotsp.h s0, s1, s22813# CHECK-INSTR: cv.sdotsp.h s0, s1, s22814# CHECK-ENCODING: [0x7b,0x84,0x24,0xa9]2815# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2816 2817//===----------------------------------------------------------------------===//2818// cv.sdotsp.b2819//===----------------------------------------------------------------------===//2820 2821cv.sdotsp.b t0, t1, t22822# CHECK-INSTR: cv.sdotsp.b t0, t1, t22823# CHECK-ENCODING: [0xfb,0x12,0x73,0xa8]2824# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2825 2826cv.sdotsp.b t3, t4, t52827# CHECK-INSTR: cv.sdotsp.b t3, t4, t52828# CHECK-ENCODING: [0x7b,0x9e,0xee,0xa9]2829# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2830 2831cv.sdotsp.b a0, a1, a22832# CHECK-INSTR: cv.sdotsp.b a0, a1, a22833# CHECK-ENCODING: [0x7b,0x95,0xc5,0xa8]2834# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2835 2836cv.sdotsp.b s0, s1, s22837# CHECK-INSTR: cv.sdotsp.b s0, s1, s22838# CHECK-ENCODING: [0x7b,0x94,0x24,0xa9]2839# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2840 2841//===----------------------------------------------------------------------===//2842// cv.sdotsp.sc.h2843//===----------------------------------------------------------------------===//2844 2845cv.sdotsp.sc.h t0, t1, t22846# CHECK-INSTR: cv.sdotsp.sc.h t0, t1, t22847# CHECK-ENCODING: [0xfb,0x42,0x73,0xa8]2848# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2849 2850cv.sdotsp.sc.h t3, t4, t52851# CHECK-INSTR: cv.sdotsp.sc.h t3, t4, t52852# CHECK-ENCODING: [0x7b,0xce,0xee,0xa9]2853# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2854 2855cv.sdotsp.sc.h a0, a1, a22856# CHECK-INSTR: cv.sdotsp.sc.h a0, a1, a22857# CHECK-ENCODING: [0x7b,0xc5,0xc5,0xa8]2858# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2859 2860cv.sdotsp.sc.h s0, s1, s22861# CHECK-INSTR: cv.sdotsp.sc.h s0, s1, s22862# CHECK-ENCODING: [0x7b,0xc4,0x24,0xa9]2863# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2864 2865//===----------------------------------------------------------------------===//2866// cv.sdotsp.sc.b2867//===----------------------------------------------------------------------===//2868 2869cv.sdotsp.sc.b t0, t1, t22870# CHECK-INSTR: cv.sdotsp.sc.b t0, t1, t22871# CHECK-ENCODING: [0xfb,0x52,0x73,0xa8]2872# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2873 2874cv.sdotsp.sc.b t3, t4, t52875# CHECK-INSTR: cv.sdotsp.sc.b t3, t4, t52876# CHECK-ENCODING: [0x7b,0xde,0xee,0xa9]2877# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2878 2879cv.sdotsp.sc.b a0, a1, a22880# CHECK-INSTR: cv.sdotsp.sc.b a0, a1, a22881# CHECK-ENCODING: [0x7b,0xd5,0xc5,0xa8]2882# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2883 2884cv.sdotsp.sc.b s0, s1, s22885# CHECK-INSTR: cv.sdotsp.sc.b s0, s1, s22886# CHECK-ENCODING: [0x7b,0xd4,0x24,0xa9]2887# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2888 2889//===----------------------------------------------------------------------===//2890// cv.sdotsp.sci.h2891//===----------------------------------------------------------------------===//2892 2893cv.sdotsp.sci.h t0, t1, 02894# CHECK-INSTR: cv.sdotsp.sci.h t0, t1, 02895# CHECK-ENCODING: [0xfb,0x62,0x03,0xa8]2896# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2897 2898cv.sdotsp.sci.h t3, t4, -322899# CHECK-INSTR: cv.sdotsp.sci.h t3, t4, -322900# CHECK-ENCODING: [0x7b,0xee,0x0e,0xa9]2901# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2902 2903cv.sdotsp.sci.h a0, a1, 72904# CHECK-INSTR: cv.sdotsp.sci.h a0, a1, 72905# CHECK-ENCODING: [0x7b,0xe5,0x35,0xaa]2906# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2907 2908cv.sdotsp.sci.h s0, s1, -12909# CHECK-INSTR: cv.sdotsp.sci.h s0, s1, -12910# CHECK-ENCODING: [0x7b,0xe4,0xf4,0xab]2911# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2912 2913//===----------------------------------------------------------------------===//2914// cv.sdotsp.sci.b2915//===----------------------------------------------------------------------===//2916 2917cv.sdotsp.sci.b t0, t1, 02918# CHECK-INSTR: cv.sdotsp.sci.b t0, t1, 02919# CHECK-ENCODING: [0xfb,0x72,0x03,0xa8]2920# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2921 2922cv.sdotsp.sci.b t3, t4, -322923# CHECK-INSTR: cv.sdotsp.sci.b t3, t4, -322924# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xa9]2925# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2926 2927cv.sdotsp.sci.b a0, a1, 72928# CHECK-INSTR: cv.sdotsp.sci.b a0, a1, 72929# CHECK-ENCODING: [0x7b,0xf5,0x35,0xaa]2930# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2931 2932cv.sdotsp.sci.b s0, s1, -12933# CHECK-INSTR: cv.sdotsp.sci.b s0, s1, -12934# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xab]2935# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2936 2937//===----------------------------------------------------------------------===//2938// cv.extract.h2939//===----------------------------------------------------------------------===//2940 2941cv.extract.h t0, t1, 02942# CHECK-INSTR: cv.extract.h t0, t1, 02943# CHECK-ENCODING: [0xfb,0x02,0x03,0xb8]2944# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2945 2946cv.extract.h t3, t4, 322947# CHECK-INSTR: cv.extract.h t3, t4, 322948# CHECK-ENCODING: [0x7b,0x8e,0x0e,0xb9]2949# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2950 2951cv.extract.h a0, a1, 72952# CHECK-INSTR: cv.extract.h a0, a1, 72953# CHECK-ENCODING: [0x7b,0x85,0x35,0xba]2954# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2955 2956cv.extract.h s0, s1, 632957# CHECK-INSTR: cv.extract.h s0, s1, 632958# CHECK-ENCODING: [0x7b,0x84,0xf4,0xbb]2959# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2960 2961//===----------------------------------------------------------------------===//2962// cv.extract.b2963//===----------------------------------------------------------------------===//2964 2965cv.extract.b t0, t1, 02966# CHECK-INSTR: cv.extract.b t0, t1, 02967# CHECK-ENCODING: [0xfb,0x12,0x03,0xb8]2968# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2969 2970cv.extract.b t3, t4, 322971# CHECK-INSTR: cv.extract.b t3, t4, 322972# CHECK-ENCODING: [0x7b,0x9e,0x0e,0xb9]2973# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2974 2975cv.extract.b a0, a1, 72976# CHECK-INSTR: cv.extract.b a0, a1, 72977# CHECK-ENCODING: [0x7b,0x95,0x35,0xba]2978# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2979 2980cv.extract.b s0, s1, 632981# CHECK-INSTR: cv.extract.b s0, s1, 632982# CHECK-ENCODING: [0x7b,0x94,0xf4,0xbb]2983# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2984 2985//===----------------------------------------------------------------------===//2986// cv.extractu.h2987//===----------------------------------------------------------------------===//2988 2989cv.extractu.h t0, t1, 02990# CHECK-INSTR: cv.extractu.h t0, t1, 02991# CHECK-ENCODING: [0xfb,0x22,0x03,0xb8]2992# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2993 2994cv.extractu.h t3, t4, 322995# CHECK-INSTR: cv.extractu.h t3, t4, 322996# CHECK-ENCODING: [0x7b,0xae,0x0e,0xb9]2997# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}2998 2999cv.extractu.h a0, a1, 73000# CHECK-INSTR: cv.extractu.h a0, a1, 73001# CHECK-ENCODING: [0x7b,0xa5,0x35,0xba]3002# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3003 3004cv.extractu.h s0, s1, 633005# CHECK-INSTR: cv.extractu.h s0, s1, 633006# CHECK-ENCODING: [0x7b,0xa4,0xf4,0xbb]3007# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3008 3009//===----------------------------------------------------------------------===//3010// cv.extractu.b3011//===----------------------------------------------------------------------===//3012 3013cv.extractu.b t0, t1, 03014# CHECK-INSTR: cv.extractu.b t0, t1, 03015# CHECK-ENCODING: [0xfb,0x32,0x03,0xb8]3016# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3017 3018cv.extractu.b t3, t4, 323019# CHECK-INSTR: cv.extractu.b t3, t4, 323020# CHECK-ENCODING: [0x7b,0xbe,0x0e,0xb9]3021# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3022 3023cv.extractu.b a0, a1, 73024# CHECK-INSTR: cv.extractu.b a0, a1, 73025# CHECK-ENCODING: [0x7b,0xb5,0x35,0xba]3026# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3027 3028cv.extractu.b s0, s1, 633029# CHECK-INSTR: cv.extractu.b s0, s1, 633030# CHECK-ENCODING: [0x7b,0xb4,0xf4,0xbb]3031# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3032 3033//===----------------------------------------------------------------------===//3034// cv.insert.h3035//===----------------------------------------------------------------------===//3036 3037cv.insert.h t0, t1, 03038# CHECK-INSTR: cv.insert.h t0, t1, 03039# CHECK-ENCODING: [0xfb,0x42,0x03,0xb8]3040# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3041 3042cv.insert.h t3, t4, 323043# CHECK-INSTR: cv.insert.h t3, t4, 323044# CHECK-ENCODING: [0x7b,0xce,0x0e,0xb9]3045# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3046 3047cv.insert.h a0, a1, 73048# CHECK-INSTR: cv.insert.h a0, a1, 73049# CHECK-ENCODING: [0x7b,0xc5,0x35,0xba]3050# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3051 3052cv.insert.h s0, s1, 633053# CHECK-INSTR: cv.insert.h s0, s1, 633054# CHECK-ENCODING: [0x7b,0xc4,0xf4,0xbb]3055# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3056 3057//===----------------------------------------------------------------------===//3058// cv.insert.b3059//===----------------------------------------------------------------------===//3060 3061cv.insert.b t0, t1, 03062# CHECK-INSTR: cv.insert.b t0, t1, 03063# CHECK-ENCODING: [0xfb,0x52,0x03,0xb8]3064# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3065 3066cv.insert.b t3, t4, 323067# CHECK-INSTR: cv.insert.b t3, t4, 323068# CHECK-ENCODING: [0x7b,0xde,0x0e,0xb9]3069# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3070 3071cv.insert.b a0, a1, 73072# CHECK-INSTR: cv.insert.b a0, a1, 73073# CHECK-ENCODING: [0x7b,0xd5,0x35,0xba]3074# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3075 3076cv.insert.b s0, s1, 633077# CHECK-INSTR: cv.insert.b s0, s1, 633078# CHECK-ENCODING: [0x7b,0xd4,0xf4,0xbb]3079# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3080 3081//===----------------------------------------------------------------------===//3082// cv.shuffle.h3083//===----------------------------------------------------------------------===//3084 3085cv.shuffle.h t0, t1, t23086# CHECK-INSTR: cv.shuffle.h t0, t1, t23087# CHECK-ENCODING: [0xfb,0x02,0x73,0xc0]3088# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3089 3090cv.shuffle.h t3, t4, t53091# CHECK-INSTR: cv.shuffle.h t3, t4, t53092# CHECK-ENCODING: [0x7b,0x8e,0xee,0xc1]3093# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3094 3095cv.shuffle.h a0, a1, a23096# CHECK-INSTR: cv.shuffle.h a0, a1, a23097# CHECK-ENCODING: [0x7b,0x85,0xc5,0xc0]3098# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3099 3100cv.shuffle.h s0, s1, s23101# CHECK-INSTR: cv.shuffle.h s0, s1, s23102# CHECK-ENCODING: [0x7b,0x84,0x24,0xc1]3103# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3104 3105//===----------------------------------------------------------------------===//3106// cv.shuffle.b3107//===----------------------------------------------------------------------===//3108 3109cv.shuffle.b t0, t1, t23110# CHECK-INSTR: cv.shuffle.b t0, t1, t23111# CHECK-ENCODING: [0xfb,0x12,0x73,0xc0]3112# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3113 3114cv.shuffle.b t3, t4, t53115# CHECK-INSTR: cv.shuffle.b t3, t4, t53116# CHECK-ENCODING: [0x7b,0x9e,0xee,0xc1]3117# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3118 3119cv.shuffle.b a0, a1, a23120# CHECK-INSTR: cv.shuffle.b a0, a1, a23121# CHECK-ENCODING: [0x7b,0x95,0xc5,0xc0]3122# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3123 3124cv.shuffle.b s0, s1, s23125# CHECK-INSTR: cv.shuffle.b s0, s1, s23126# CHECK-ENCODING: [0x7b,0x94,0x24,0xc1]3127# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3128 3129//===----------------------------------------------------------------------===//3130// cv.shuffle.sci.h3131//===----------------------------------------------------------------------===//3132 3133cv.shuffle.sci.h t0, t1, 03134# CHECK-INSTR: cv.shuffle.sci.h t0, t1, 03135# CHECK-ENCODING: [0xfb,0x62,0x03,0xc0]3136# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3137 3138cv.shuffle.sci.h t3, t4, 323139# CHECK-INSTR: cv.shuffle.sci.h t3, t4, 323140# CHECK-ENCODING: [0x7b,0xee,0x0e,0xc1]3141# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3142 3143cv.shuffle.sci.h a0, a1, 73144# CHECK-INSTR: cv.shuffle.sci.h a0, a1, 73145# CHECK-ENCODING: [0x7b,0xe5,0x35,0xc2]3146# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3147 3148cv.shuffle.sci.h s0, s1, 633149# CHECK-INSTR: cv.shuffle.sci.h s0, s1, 633150# CHECK-ENCODING: [0x7b,0xe4,0xf4,0xc3]3151# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3152 3153//===----------------------------------------------------------------------===//3154// cv.shuffleI0.sci.b3155//===----------------------------------------------------------------------===//3156 3157cv.shufflei0.sci.b t0, t1, 03158# CHECK-INSTR: cv.shufflei0.sci.b t0, t1, 03159# CHECK-ENCODING: [0xfb,0x72,0x03,0xc0]3160# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3161 3162cv.shufflei0.sci.b t3, t4, 323163# CHECK-INSTR: cv.shufflei0.sci.b t3, t4, 323164# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xc1]3165# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3166 3167cv.shufflei0.sci.b a0, a1, 73168# CHECK-INSTR: cv.shufflei0.sci.b a0, a1, 73169# CHECK-ENCODING: [0x7b,0xf5,0x35,0xc2]3170# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3171 3172cv.shufflei0.sci.b s0, s1, 633173# CHECK-INSTR: cv.shufflei0.sci.b s0, s1, 633174# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xc3]3175# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3176 3177//===----------------------------------------------------------------------===//3178// cv.shuffleI1.sci.b3179//===----------------------------------------------------------------------===//3180 3181cv.shufflei1.sci.b t0, t1, 03182# CHECK-INSTR: cv.shufflei1.sci.b t0, t1, 03183# CHECK-ENCODING: [0xfb,0x72,0x03,0xc8]3184# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3185 3186cv.shufflei1.sci.b t3, t4, 323187# CHECK-INSTR: cv.shufflei1.sci.b t3, t4, 323188# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xc9]3189# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3190 3191cv.shufflei1.sci.b a0, a1, 73192# CHECK-INSTR: cv.shufflei1.sci.b a0, a1, 73193# CHECK-ENCODING: [0x7b,0xf5,0x35,0xca]3194# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3195 3196cv.shufflei1.sci.b s0, s1, 633197# CHECK-INSTR: cv.shufflei1.sci.b s0, s1, 633198# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xcb]3199# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3200 3201//===----------------------------------------------------------------------===//3202// cv.shuffleI2.sci.b3203//===----------------------------------------------------------------------===//3204 3205cv.shufflei2.sci.b t0, t1, 03206# CHECK-INSTR: cv.shufflei2.sci.b t0, t1, 03207# CHECK-ENCODING: [0xfb,0x72,0x03,0xd0]3208# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3209 3210cv.shufflei2.sci.b t3, t4, 323211# CHECK-INSTR: cv.shufflei2.sci.b t3, t4, 323212# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xd1]3213# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3214 3215cv.shufflei2.sci.b a0, a1, 73216# CHECK-INSTR: cv.shufflei2.sci.b a0, a1, 73217# CHECK-ENCODING: [0x7b,0xf5,0x35,0xd2]3218# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3219 3220cv.shufflei2.sci.b s0, s1, 633221# CHECK-INSTR: cv.shufflei2.sci.b s0, s1, 633222# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xd3]3223# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3224 3225//===----------------------------------------------------------------------===//3226// cv.shuffleI3.sci.b3227//===----------------------------------------------------------------------===//3228 3229cv.shufflei3.sci.b t0, t1, 03230# CHECK-INSTR: cv.shufflei3.sci.b t0, t1, 03231# CHECK-ENCODING: [0xfb,0x72,0x03,0xd8]3232# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3233 3234cv.shufflei3.sci.b t3, t4, 323235# CHECK-INSTR: cv.shufflei3.sci.b t3, t4, 323236# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xd9]3237# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3238 3239cv.shufflei3.sci.b a0, a1, 73240# CHECK-INSTR: cv.shufflei3.sci.b a0, a1, 73241# CHECK-ENCODING: [0x7b,0xf5,0x35,0xda]3242# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3243 3244cv.shufflei3.sci.b s0, s1, 633245# CHECK-INSTR: cv.shufflei3.sci.b s0, s1, 633246# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xdb]3247# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3248 3249//===----------------------------------------------------------------------===//3250// cv.shuffle2.h3251//===----------------------------------------------------------------------===//3252 3253cv.shuffle2.h t0, t1, t23254# CHECK-INSTR: cv.shuffle2.h t0, t1, t23255# CHECK-ENCODING: [0xfb,0x02,0x73,0xe0]3256# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3257 3258cv.shuffle2.h t3, t4, t53259# CHECK-INSTR: cv.shuffle2.h t3, t4, t53260# CHECK-ENCODING: [0x7b,0x8e,0xee,0xe1]3261# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3262 3263cv.shuffle2.h a0, a1, a23264# CHECK-INSTR: cv.shuffle2.h a0, a1, a23265# CHECK-ENCODING: [0x7b,0x85,0xc5,0xe0]3266# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3267 3268cv.shuffle2.h s0, s1, s23269# CHECK-INSTR: cv.shuffle2.h s0, s1, s23270# CHECK-ENCODING: [0x7b,0x84,0x24,0xe1]3271# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3272 3273//===----------------------------------------------------------------------===//3274// cv.shuffle2.b3275//===----------------------------------------------------------------------===//3276 3277cv.shuffle2.b t0, t1, t23278# CHECK-INSTR: cv.shuffle2.b t0, t1, t23279# CHECK-ENCODING: [0xfb,0x12,0x73,0xe0]3280# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3281 3282cv.shuffle2.b t3, t4, t53283# CHECK-INSTR: cv.shuffle2.b t3, t4, t53284# CHECK-ENCODING: [0x7b,0x9e,0xee,0xe1]3285# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3286 3287cv.shuffle2.b a0, a1, a23288# CHECK-INSTR: cv.shuffle2.b a0, a1, a23289# CHECK-ENCODING: [0x7b,0x95,0xc5,0xe0]3290# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3291 3292cv.shuffle2.b s0, s1, s23293# CHECK-INSTR: cv.shuffle2.b s0, s1, s23294# CHECK-ENCODING: [0x7b,0x94,0x24,0xe1]3295# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3296 3297//===----------------------------------------------------------------------===//3298// cv.pack3299//===----------------------------------------------------------------------===//3300 3301cv.pack t0, t1, t23302# CHECK-INSTR: cv.pack t0, t1, t23303# CHECK-ENCODING: [0xfb,0x02,0x73,0xf0]3304# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3305 3306cv.pack t3, t4, t53307# CHECK-INSTR: cv.pack t3, t4, t53308# CHECK-ENCODING: [0x7b,0x8e,0xee,0xf1]3309# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3310 3311cv.pack a0, a1, a23312# CHECK-INSTR: cv.pack a0, a1, a23313# CHECK-ENCODING: [0x7b,0x85,0xc5,0xf0]3314# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3315 3316cv.pack s0, s1, s23317# CHECK-INSTR: cv.pack s0, s1, s23318# CHECK-ENCODING: [0x7b,0x84,0x24,0xf1]3319# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3320 3321//===----------------------------------------------------------------------===//3322// cv.pack.h3323//===----------------------------------------------------------------------===//3324 3325cv.pack.h t0, t1, t23326# CHECK-INSTR: cv.pack.h t0, t1, t23327# CHECK-ENCODING: [0xfb,0x02,0x73,0xf2]3328# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3329 3330cv.pack.h t3, t4, t53331# CHECK-INSTR: cv.pack.h t3, t4, t53332# CHECK-ENCODING: [0x7b,0x8e,0xee,0xf3]3333# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3334 3335cv.pack.h a0, a1, a23336# CHECK-INSTR: cv.pack.h a0, a1, a23337# CHECK-ENCODING: [0x7b,0x85,0xc5,0xf2]3338# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3339 3340cv.pack.h s0, s1, s23341# CHECK-INSTR: cv.pack.h s0, s1, s23342# CHECK-ENCODING: [0x7b,0x84,0x24,0xf3]3343# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3344 3345//===----------------------------------------------------------------------===//3346// cv.packhi.b3347//===----------------------------------------------------------------------===//3348 3349cv.packhi.b t0, t1, t23350# CHECK-INSTR: cv.packhi.b t0, t1, t23351# CHECK-ENCODING: [0xfb,0x12,0x73,0xfa]3352# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3353 3354cv.packhi.b t3, t4, t53355# CHECK-INSTR: cv.packhi.b t3, t4, t53356# CHECK-ENCODING: [0x7b,0x9e,0xee,0xfb]3357# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3358 3359cv.packhi.b a0, a1, a23360# CHECK-INSTR: cv.packhi.b a0, a1, a23361# CHECK-ENCODING: [0x7b,0x95,0xc5,0xfa]3362# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3363 3364cv.packhi.b s0, s1, s23365# CHECK-INSTR: cv.packhi.b s0, s1, s23366# CHECK-ENCODING: [0x7b,0x94,0x24,0xfb]3367# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3368 3369//===----------------------------------------------------------------------===//3370// cv.packlo.b3371//===----------------------------------------------------------------------===//3372 3373cv.packlo.b t0, t1, t23374# CHECK-INSTR: cv.packlo.b t0, t1, t23375# CHECK-ENCODING: [0xfb,0x12,0x73,0xf8]3376# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3377 3378cv.packlo.b t3, t4, t53379# CHECK-INSTR: cv.packlo.b t3, t4, t53380# CHECK-ENCODING: [0x7b,0x9e,0xee,0xf9]3381# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3382 3383cv.packlo.b a0, a1, a23384# CHECK-INSTR: cv.packlo.b a0, a1, a23385# CHECK-ENCODING: [0x7b,0x95,0xc5,0xf8]3386# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3387 3388cv.packlo.b s0, s1, s23389# CHECK-INSTR: cv.packlo.b s0, s1, s23390# CHECK-ENCODING: [0x7b,0x94,0x24,0xf9]3391# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3392 3393//===----------------------------------------------------------------------===//3394// cv.cmpeq.h3395//===----------------------------------------------------------------------===//3396 3397cv.cmpeq.h t0, t1, t23398# CHECK-INSTR: cv.cmpeq.h t0, t1, t23399# CHECK-ENCODING: [0xfb,0x02,0x73,0x04]3400# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3401 3402cv.cmpeq.h t3, t4, t53403# CHECK-INSTR: cv.cmpeq.h t3, t4, t53404# CHECK-ENCODING: [0x7b,0x8e,0xee,0x05]3405# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3406 3407cv.cmpeq.h a0, a1, a23408# CHECK-INSTR: cv.cmpeq.h a0, a1, a23409# CHECK-ENCODING: [0x7b,0x85,0xc5,0x04]3410# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3411 3412cv.cmpeq.h s0, s1, s23413# CHECK-INSTR: cv.cmpeq.h s0, s1, s23414# CHECK-ENCODING: [0x7b,0x84,0x24,0x05]3415# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3416 3417//===----------------------------------------------------------------------===//3418// cv.cmpeq.b3419//===----------------------------------------------------------------------===//3420 3421cv.cmpeq.b t0, t1, t23422# CHECK-INSTR: cv.cmpeq.b t0, t1, t23423# CHECK-ENCODING: [0xfb,0x12,0x73,0x04]3424# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3425 3426cv.cmpeq.b t3, t4, t53427# CHECK-INSTR: cv.cmpeq.b t3, t4, t53428# CHECK-ENCODING: [0x7b,0x9e,0xee,0x05]3429# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3430 3431cv.cmpeq.b a0, a1, a23432# CHECK-INSTR: cv.cmpeq.b a0, a1, a23433# CHECK-ENCODING: [0x7b,0x95,0xc5,0x04]3434# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3435 3436cv.cmpeq.b s0, s1, s23437# CHECK-INSTR: cv.cmpeq.b s0, s1, s23438# CHECK-ENCODING: [0x7b,0x94,0x24,0x05]3439# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3440 3441//===----------------------------------------------------------------------===//3442// cv.cmpeq.sc.h3443//===----------------------------------------------------------------------===//3444 3445cv.cmpeq.sc.h t0, t1, t23446# CHECK-INSTR: cv.cmpeq.sc.h t0, t1, t23447# CHECK-ENCODING: [0xfb,0x42,0x73,0x04]3448# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3449 3450cv.cmpeq.sc.h t3, t4, t53451# CHECK-INSTR: cv.cmpeq.sc.h t3, t4, t53452# CHECK-ENCODING: [0x7b,0xce,0xee,0x05]3453# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3454 3455cv.cmpeq.sc.h a0, a1, a23456# CHECK-INSTR: cv.cmpeq.sc.h a0, a1, a23457# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x04]3458# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3459 3460cv.cmpeq.sc.h s0, s1, s23461# CHECK-INSTR: cv.cmpeq.sc.h s0, s1, s23462# CHECK-ENCODING: [0x7b,0xc4,0x24,0x05]3463# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3464 3465//===----------------------------------------------------------------------===//3466// cv.cmpeq.sc.b3467//===----------------------------------------------------------------------===//3468 3469cv.cmpeq.sc.b t0, t1, t23470# CHECK-INSTR: cv.cmpeq.sc.b t0, t1, t23471# CHECK-ENCODING: [0xfb,0x52,0x73,0x04]3472# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3473 3474cv.cmpeq.sc.b t3, t4, t53475# CHECK-INSTR: cv.cmpeq.sc.b t3, t4, t53476# CHECK-ENCODING: [0x7b,0xde,0xee,0x05]3477# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3478 3479cv.cmpeq.sc.b a0, a1, a23480# CHECK-INSTR: cv.cmpeq.sc.b a0, a1, a23481# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x04]3482# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3483 3484cv.cmpeq.sc.b s0, s1, s23485# CHECK-INSTR: cv.cmpeq.sc.b s0, s1, s23486# CHECK-ENCODING: [0x7b,0xd4,0x24,0x05]3487# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3488 3489//===----------------------------------------------------------------------===//3490// cv.cmpeq.sci.h3491//===----------------------------------------------------------------------===//3492 3493cv.cmpeq.sci.h t0, t1, 03494# CHECK-INSTR: cv.cmpeq.sci.h t0, t1, 03495# CHECK-ENCODING: [0xfb,0x62,0x03,0x04]3496# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3497 3498cv.cmpeq.sci.h t3, t4, -323499# CHECK-INSTR: cv.cmpeq.sci.h t3, t4, -323500# CHECK-ENCODING: [0x7b,0xee,0x0e,0x05]3501# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3502 3503cv.cmpeq.sci.h a0, a1, 73504# CHECK-INSTR: cv.cmpeq.sci.h a0, a1, 73505# CHECK-ENCODING: [0x7b,0xe5,0x35,0x06]3506# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3507 3508cv.cmpeq.sci.h s0, s1, -13509# CHECK-INSTR: cv.cmpeq.sci.h s0, s1, -13510# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x07]3511# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3512 3513//===----------------------------------------------------------------------===//3514// cv.cmpeq.sci.b3515//===----------------------------------------------------------------------===//3516 3517cv.cmpeq.sci.b t0, t1, 03518# CHECK-INSTR: cv.cmpeq.sci.b t0, t1, 03519# CHECK-ENCODING: [0xfb,0x72,0x03,0x04]3520# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3521 3522cv.cmpeq.sci.b t3, t4, -323523# CHECK-INSTR: cv.cmpeq.sci.b t3, t4, -323524# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x05]3525# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3526 3527cv.cmpeq.sci.b a0, a1, 73528# CHECK-INSTR: cv.cmpeq.sci.b a0, a1, 73529# CHECK-ENCODING: [0x7b,0xf5,0x35,0x06]3530# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3531 3532cv.cmpeq.sci.b s0, s1, -13533# CHECK-INSTR: cv.cmpeq.sci.b s0, s1, -13534# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x07]3535# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3536 3537//===----------------------------------------------------------------------===//3538// cv.cmpne.h3539//===----------------------------------------------------------------------===//3540 3541cv.cmpne.h t0, t1, t23542# CHECK-INSTR: cv.cmpne.h t0, t1, t23543# CHECK-ENCODING: [0xfb,0x02,0x73,0x0c]3544# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3545 3546cv.cmpne.h t3, t4, t53547# CHECK-INSTR: cv.cmpne.h t3, t4, t53548# CHECK-ENCODING: [0x7b,0x8e,0xee,0x0d]3549# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3550 3551cv.cmpne.h a0, a1, a23552# CHECK-INSTR: cv.cmpne.h a0, a1, a23553# CHECK-ENCODING: [0x7b,0x85,0xc5,0x0c]3554# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3555 3556cv.cmpne.h s0, s1, s23557# CHECK-INSTR: cv.cmpne.h s0, s1, s23558# CHECK-ENCODING: [0x7b,0x84,0x24,0x0d]3559# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3560 3561//===----------------------------------------------------------------------===//3562// cv.cmpne.b3563//===----------------------------------------------------------------------===//3564 3565cv.cmpne.b t0, t1, t23566# CHECK-INSTR: cv.cmpne.b t0, t1, t23567# CHECK-ENCODING: [0xfb,0x12,0x73,0x0c]3568# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3569 3570cv.cmpne.b t3, t4, t53571# CHECK-INSTR: cv.cmpne.b t3, t4, t53572# CHECK-ENCODING: [0x7b,0x9e,0xee,0x0d]3573# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3574 3575cv.cmpne.b a0, a1, a23576# CHECK-INSTR: cv.cmpne.b a0, a1, a23577# CHECK-ENCODING: [0x7b,0x95,0xc5,0x0c]3578# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3579 3580cv.cmpne.b s0, s1, s23581# CHECK-INSTR: cv.cmpne.b s0, s1, s23582# CHECK-ENCODING: [0x7b,0x94,0x24,0x0d]3583# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3584 3585//===----------------------------------------------------------------------===//3586// cv.cmpne.sc.h3587//===----------------------------------------------------------------------===//3588 3589cv.cmpne.sc.h t0, t1, t23590# CHECK-INSTR: cv.cmpne.sc.h t0, t1, t23591# CHECK-ENCODING: [0xfb,0x42,0x73,0x0c]3592# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3593 3594cv.cmpne.sc.h t3, t4, t53595# CHECK-INSTR: cv.cmpne.sc.h t3, t4, t53596# CHECK-ENCODING: [0x7b,0xce,0xee,0x0d]3597# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3598 3599cv.cmpne.sc.h a0, a1, a23600# CHECK-INSTR: cv.cmpne.sc.h a0, a1, a23601# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x0c]3602# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3603 3604cv.cmpne.sc.h s0, s1, s23605# CHECK-INSTR: cv.cmpne.sc.h s0, s1, s23606# CHECK-ENCODING: [0x7b,0xc4,0x24,0x0d]3607# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3608 3609//===----------------------------------------------------------------------===//3610// cv.cmpne.sc.b3611//===----------------------------------------------------------------------===//3612 3613cv.cmpne.sc.b t0, t1, t23614# CHECK-INSTR: cv.cmpne.sc.b t0, t1, t23615# CHECK-ENCODING: [0xfb,0x52,0x73,0x0c]3616# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3617 3618cv.cmpne.sc.b t3, t4, t53619# CHECK-INSTR: cv.cmpne.sc.b t3, t4, t53620# CHECK-ENCODING: [0x7b,0xde,0xee,0x0d]3621# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3622 3623cv.cmpne.sc.b a0, a1, a23624# CHECK-INSTR: cv.cmpne.sc.b a0, a1, a23625# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x0c]3626# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3627 3628cv.cmpne.sc.b s0, s1, s23629# CHECK-INSTR: cv.cmpne.sc.b s0, s1, s23630# CHECK-ENCODING: [0x7b,0xd4,0x24,0x0d]3631# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3632 3633//===----------------------------------------------------------------------===//3634// cv.cmpne.sci.h3635//===----------------------------------------------------------------------===//3636 3637cv.cmpne.sci.h t0, t1, 03638# CHECK-INSTR: cv.cmpne.sci.h t0, t1, 03639# CHECK-ENCODING: [0xfb,0x62,0x03,0x0c]3640# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3641 3642cv.cmpne.sci.h t3, t4, -323643# CHECK-INSTR: cv.cmpne.sci.h t3, t4, -323644# CHECK-ENCODING: [0x7b,0xee,0x0e,0x0d]3645# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3646 3647cv.cmpne.sci.h a0, a1, 73648# CHECK-INSTR: cv.cmpne.sci.h a0, a1, 73649# CHECK-ENCODING: [0x7b,0xe5,0x35,0x0e]3650# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3651 3652cv.cmpne.sci.h s0, s1, -13653# CHECK-INSTR: cv.cmpne.sci.h s0, s1, -13654# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x0f]3655# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3656 3657//===----------------------------------------------------------------------===//3658// cv.cmpne.sci.b3659//===----------------------------------------------------------------------===//3660 3661cv.cmpne.sci.b t0, t1, 03662# CHECK-INSTR: cv.cmpne.sci.b t0, t1, 03663# CHECK-ENCODING: [0xfb,0x72,0x03,0x0c]3664# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3665 3666cv.cmpne.sci.b t3, t4, -323667# CHECK-INSTR: cv.cmpne.sci.b t3, t4, -323668# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x0d]3669# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3670 3671cv.cmpne.sci.b a0, a1, 73672# CHECK-INSTR: cv.cmpne.sci.b a0, a1, 73673# CHECK-ENCODING: [0x7b,0xf5,0x35,0x0e]3674# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3675 3676cv.cmpne.sci.b s0, s1, -13677# CHECK-INSTR: cv.cmpne.sci.b s0, s1, -13678# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x0f]3679# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3680 3681//===----------------------------------------------------------------------===//3682// cv.cmpgt.h3683//===----------------------------------------------------------------------===//3684 3685cv.cmpgt.h t0, t1, t23686# CHECK-INSTR: cv.cmpgt.h t0, t1, t23687# CHECK-ENCODING: [0xfb,0x02,0x73,0x14]3688# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3689 3690cv.cmpgt.h t3, t4, t53691# CHECK-INSTR: cv.cmpgt.h t3, t4, t53692# CHECK-ENCODING: [0x7b,0x8e,0xee,0x15]3693# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3694 3695cv.cmpgt.h a0, a1, a23696# CHECK-INSTR: cv.cmpgt.h a0, a1, a23697# CHECK-ENCODING: [0x7b,0x85,0xc5,0x14]3698# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3699 3700cv.cmpgt.h s0, s1, s23701# CHECK-INSTR: cv.cmpgt.h s0, s1, s23702# CHECK-ENCODING: [0x7b,0x84,0x24,0x15]3703# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3704 3705//===----------------------------------------------------------------------===//3706// cv.cmpgt.b3707//===----------------------------------------------------------------------===//3708 3709cv.cmpgt.b t0, t1, t23710# CHECK-INSTR: cv.cmpgt.b t0, t1, t23711# CHECK-ENCODING: [0xfb,0x12,0x73,0x14]3712# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3713 3714cv.cmpgt.b t3, t4, t53715# CHECK-INSTR: cv.cmpgt.b t3, t4, t53716# CHECK-ENCODING: [0x7b,0x9e,0xee,0x15]3717# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3718 3719cv.cmpgt.b a0, a1, a23720# CHECK-INSTR: cv.cmpgt.b a0, a1, a23721# CHECK-ENCODING: [0x7b,0x95,0xc5,0x14]3722# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3723 3724cv.cmpgt.b s0, s1, s23725# CHECK-INSTR: cv.cmpgt.b s0, s1, s23726# CHECK-ENCODING: [0x7b,0x94,0x24,0x15]3727# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3728 3729//===----------------------------------------------------------------------===//3730// cv.cmpgt.sc.h3731//===----------------------------------------------------------------------===//3732 3733cv.cmpgt.sc.h t0, t1, t23734# CHECK-INSTR: cv.cmpgt.sc.h t0, t1, t23735# CHECK-ENCODING: [0xfb,0x42,0x73,0x14]3736# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3737 3738cv.cmpgt.sc.h t3, t4, t53739# CHECK-INSTR: cv.cmpgt.sc.h t3, t4, t53740# CHECK-ENCODING: [0x7b,0xce,0xee,0x15]3741# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3742 3743cv.cmpgt.sc.h a0, a1, a23744# CHECK-INSTR: cv.cmpgt.sc.h a0, a1, a23745# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x14]3746# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3747 3748cv.cmpgt.sc.h s0, s1, s23749# CHECK-INSTR: cv.cmpgt.sc.h s0, s1, s23750# CHECK-ENCODING: [0x7b,0xc4,0x24,0x15]3751# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3752 3753//===----------------------------------------------------------------------===//3754// cv.cmpgt.sc.b3755//===----------------------------------------------------------------------===//3756 3757cv.cmpgt.sc.b t0, t1, t23758# CHECK-INSTR: cv.cmpgt.sc.b t0, t1, t23759# CHECK-ENCODING: [0xfb,0x52,0x73,0x14]3760# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3761 3762cv.cmpgt.sc.b t3, t4, t53763# CHECK-INSTR: cv.cmpgt.sc.b t3, t4, t53764# CHECK-ENCODING: [0x7b,0xde,0xee,0x15]3765# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3766 3767cv.cmpgt.sc.b a0, a1, a23768# CHECK-INSTR: cv.cmpgt.sc.b a0, a1, a23769# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x14]3770# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3771 3772cv.cmpgt.sc.b s0, s1, s23773# CHECK-INSTR: cv.cmpgt.sc.b s0, s1, s23774# CHECK-ENCODING: [0x7b,0xd4,0x24,0x15]3775# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3776 3777//===----------------------------------------------------------------------===//3778// cv.cmpgt.sci.h3779//===----------------------------------------------------------------------===//3780 3781cv.cmpgt.sci.h t0, t1, 03782# CHECK-INSTR: cv.cmpgt.sci.h t0, t1, 03783# CHECK-ENCODING: [0xfb,0x62,0x03,0x14]3784# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3785 3786cv.cmpgt.sci.h t3, t4, -323787# CHECK-INSTR: cv.cmpgt.sci.h t3, t4, -323788# CHECK-ENCODING: [0x7b,0xee,0x0e,0x15]3789# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3790 3791cv.cmpgt.sci.h a0, a1, 73792# CHECK-INSTR: cv.cmpgt.sci.h a0, a1, 73793# CHECK-ENCODING: [0x7b,0xe5,0x35,0x16]3794# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3795 3796cv.cmpgt.sci.h s0, s1, -13797# CHECK-INSTR: cv.cmpgt.sci.h s0, s1, -13798# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x17]3799# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3800 3801//===----------------------------------------------------------------------===//3802// cv.cmpgt.sci.b3803//===----------------------------------------------------------------------===//3804 3805cv.cmpgt.sci.b t0, t1, 03806# CHECK-INSTR: cv.cmpgt.sci.b t0, t1, 03807# CHECK-ENCODING: [0xfb,0x72,0x03,0x14]3808# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3809 3810cv.cmpgt.sci.b t3, t4, -323811# CHECK-INSTR: cv.cmpgt.sci.b t3, t4, -323812# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x15]3813# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3814 3815cv.cmpgt.sci.b a0, a1, 73816# CHECK-INSTR: cv.cmpgt.sci.b a0, a1, 73817# CHECK-ENCODING: [0x7b,0xf5,0x35,0x16]3818# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3819 3820cv.cmpgt.sci.b s0, s1, -13821# CHECK-INSTR: cv.cmpgt.sci.b s0, s1, -13822# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x17]3823# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3824 3825//===----------------------------------------------------------------------===//3826// cv.cmpge.h3827//===----------------------------------------------------------------------===//3828 3829cv.cmpge.h t0, t1, t23830# CHECK-INSTR: cv.cmpge.h t0, t1, t23831# CHECK-ENCODING: [0xfb,0x02,0x73,0x1c]3832# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3833 3834cv.cmpge.h t3, t4, t53835# CHECK-INSTR: cv.cmpge.h t3, t4, t53836# CHECK-ENCODING: [0x7b,0x8e,0xee,0x1d]3837# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3838 3839cv.cmpge.h a0, a1, a23840# CHECK-INSTR: cv.cmpge.h a0, a1, a23841# CHECK-ENCODING: [0x7b,0x85,0xc5,0x1c]3842# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3843 3844cv.cmpge.h s0, s1, s23845# CHECK-INSTR: cv.cmpge.h s0, s1, s23846# CHECK-ENCODING: [0x7b,0x84,0x24,0x1d]3847# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3848 3849//===----------------------------------------------------------------------===//3850// cv.cmpge.b3851//===----------------------------------------------------------------------===//3852 3853cv.cmpge.b t0, t1, t23854# CHECK-INSTR: cv.cmpge.b t0, t1, t23855# CHECK-ENCODING: [0xfb,0x12,0x73,0x1c]3856# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3857 3858cv.cmpge.b t3, t4, t53859# CHECK-INSTR: cv.cmpge.b t3, t4, t53860# CHECK-ENCODING: [0x7b,0x9e,0xee,0x1d]3861# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3862 3863cv.cmpge.b a0, a1, a23864# CHECK-INSTR: cv.cmpge.b a0, a1, a23865# CHECK-ENCODING: [0x7b,0x95,0xc5,0x1c]3866# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3867 3868cv.cmpge.b s0, s1, s23869# CHECK-INSTR: cv.cmpge.b s0, s1, s23870# CHECK-ENCODING: [0x7b,0x94,0x24,0x1d]3871# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3872 3873//===----------------------------------------------------------------------===//3874// cv.cmpge.sc.h3875//===----------------------------------------------------------------------===//3876 3877cv.cmpge.sc.h t0, t1, t23878# CHECK-INSTR: cv.cmpge.sc.h t0, t1, t23879# CHECK-ENCODING: [0xfb,0x42,0x73,0x1c]3880# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3881 3882cv.cmpge.sc.h t3, t4, t53883# CHECK-INSTR: cv.cmpge.sc.h t3, t4, t53884# CHECK-ENCODING: [0x7b,0xce,0xee,0x1d]3885# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3886 3887cv.cmpge.sc.h a0, a1, a23888# CHECK-INSTR: cv.cmpge.sc.h a0, a1, a23889# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x1c]3890# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3891 3892cv.cmpge.sc.h s0, s1, s23893# CHECK-INSTR: cv.cmpge.sc.h s0, s1, s23894# CHECK-ENCODING: [0x7b,0xc4,0x24,0x1d]3895# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3896 3897//===----------------------------------------------------------------------===//3898// cv.cmpge.sc.b3899//===----------------------------------------------------------------------===//3900 3901cv.cmpge.sc.b t0, t1, t23902# CHECK-INSTR: cv.cmpge.sc.b t0, t1, t23903# CHECK-ENCODING: [0xfb,0x52,0x73,0x1c]3904# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3905 3906cv.cmpge.sc.b t3, t4, t53907# CHECK-INSTR: cv.cmpge.sc.b t3, t4, t53908# CHECK-ENCODING: [0x7b,0xde,0xee,0x1d]3909# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3910 3911cv.cmpge.sc.b a0, a1, a23912# CHECK-INSTR: cv.cmpge.sc.b a0, a1, a23913# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x1c]3914# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3915 3916cv.cmpge.sc.b s0, s1, s23917# CHECK-INSTR: cv.cmpge.sc.b s0, s1, s23918# CHECK-ENCODING: [0x7b,0xd4,0x24,0x1d]3919# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3920 3921//===----------------------------------------------------------------------===//3922// cv.cmpge.sci.h3923//===----------------------------------------------------------------------===//3924 3925cv.cmpge.sci.h t0, t1, 03926# CHECK-INSTR: cv.cmpge.sci.h t0, t1, 03927# CHECK-ENCODING: [0xfb,0x62,0x03,0x1c]3928# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3929 3930cv.cmpge.sci.h t3, t4, -323931# CHECK-INSTR: cv.cmpge.sci.h t3, t4, -323932# CHECK-ENCODING: [0x7b,0xee,0x0e,0x1d]3933# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3934 3935cv.cmpge.sci.h a0, a1, 73936# CHECK-INSTR: cv.cmpge.sci.h a0, a1, 73937# CHECK-ENCODING: [0x7b,0xe5,0x35,0x1e]3938# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3939 3940cv.cmpge.sci.h s0, s1, -13941# CHECK-INSTR: cv.cmpge.sci.h s0, s1, -13942# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x1f]3943# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3944 3945//===----------------------------------------------------------------------===//3946// cv.cmpge.sci.b3947//===----------------------------------------------------------------------===//3948 3949cv.cmpge.sci.b t0, t1, 03950# CHECK-INSTR: cv.cmpge.sci.b t0, t1, 03951# CHECK-ENCODING: [0xfb,0x72,0x03,0x1c]3952# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3953 3954cv.cmpge.sci.b t3, t4, -323955# CHECK-INSTR: cv.cmpge.sci.b t3, t4, -323956# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x1d]3957# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3958 3959cv.cmpge.sci.b a0, a1, 73960# CHECK-INSTR: cv.cmpge.sci.b a0, a1, 73961# CHECK-ENCODING: [0x7b,0xf5,0x35,0x1e]3962# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3963 3964cv.cmpge.sci.b s0, s1, -13965# CHECK-INSTR: cv.cmpge.sci.b s0, s1, -13966# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x1f]3967# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3968 3969//===----------------------------------------------------------------------===//3970// cv.cmplt.h3971//===----------------------------------------------------------------------===//3972 3973cv.cmplt.h t0, t1, t23974# CHECK-INSTR: cv.cmplt.h t0, t1, t23975# CHECK-ENCODING: [0xfb,0x02,0x73,0x24]3976# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3977 3978cv.cmplt.h t3, t4, t53979# CHECK-INSTR: cv.cmplt.h t3, t4, t53980# CHECK-ENCODING: [0x7b,0x8e,0xee,0x25]3981# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3982 3983cv.cmplt.h a0, a1, a23984# CHECK-INSTR: cv.cmplt.h a0, a1, a23985# CHECK-ENCODING: [0x7b,0x85,0xc5,0x24]3986# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3987 3988cv.cmplt.h s0, s1, s23989# CHECK-INSTR: cv.cmplt.h s0, s1, s23990# CHECK-ENCODING: [0x7b,0x84,0x24,0x25]3991# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}3992 3993//===----------------------------------------------------------------------===//3994// cv.cmplt.b3995//===----------------------------------------------------------------------===//3996 3997cv.cmplt.b t0, t1, t23998# CHECK-INSTR: cv.cmplt.b t0, t1, t23999# CHECK-ENCODING: [0xfb,0x12,0x73,0x24]4000# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4001 4002cv.cmplt.b t3, t4, t54003# CHECK-INSTR: cv.cmplt.b t3, t4, t54004# CHECK-ENCODING: [0x7b,0x9e,0xee,0x25]4005# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4006 4007cv.cmplt.b a0, a1, a24008# CHECK-INSTR: cv.cmplt.b a0, a1, a24009# CHECK-ENCODING: [0x7b,0x95,0xc5,0x24]4010# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4011 4012cv.cmplt.b s0, s1, s24013# CHECK-INSTR: cv.cmplt.b s0, s1, s24014# CHECK-ENCODING: [0x7b,0x94,0x24,0x25]4015# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4016 4017//===----------------------------------------------------------------------===//4018// cv.cmplt.sc.h4019//===----------------------------------------------------------------------===//4020 4021cv.cmplt.sc.h t0, t1, t24022# CHECK-INSTR: cv.cmplt.sc.h t0, t1, t24023# CHECK-ENCODING: [0xfb,0x42,0x73,0x24]4024# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4025 4026cv.cmplt.sc.h t3, t4, t54027# CHECK-INSTR: cv.cmplt.sc.h t3, t4, t54028# CHECK-ENCODING: [0x7b,0xce,0xee,0x25]4029# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4030 4031cv.cmplt.sc.h a0, a1, a24032# CHECK-INSTR: cv.cmplt.sc.h a0, a1, a24033# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x24]4034# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4035 4036cv.cmplt.sc.h s0, s1, s24037# CHECK-INSTR: cv.cmplt.sc.h s0, s1, s24038# CHECK-ENCODING: [0x7b,0xc4,0x24,0x25]4039# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4040 4041//===----------------------------------------------------------------------===//4042// cv.cmplt.sc.b4043//===----------------------------------------------------------------------===//4044 4045cv.cmplt.sc.b t0, t1, t24046# CHECK-INSTR: cv.cmplt.sc.b t0, t1, t24047# CHECK-ENCODING: [0xfb,0x52,0x73,0x24]4048# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4049 4050cv.cmplt.sc.b t3, t4, t54051# CHECK-INSTR: cv.cmplt.sc.b t3, t4, t54052# CHECK-ENCODING: [0x7b,0xde,0xee,0x25]4053# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4054 4055cv.cmplt.sc.b a0, a1, a24056# CHECK-INSTR: cv.cmplt.sc.b a0, a1, a24057# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x24]4058# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4059 4060cv.cmplt.sc.b s0, s1, s24061# CHECK-INSTR: cv.cmplt.sc.b s0, s1, s24062# CHECK-ENCODING: [0x7b,0xd4,0x24,0x25]4063# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4064 4065//===----------------------------------------------------------------------===//4066// cv.cmplt.sci.h4067//===----------------------------------------------------------------------===//4068 4069cv.cmplt.sci.h t0, t1, 04070# CHECK-INSTR: cv.cmplt.sci.h t0, t1, 04071# CHECK-ENCODING: [0xfb,0x62,0x03,0x24]4072# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4073 4074cv.cmplt.sci.h t3, t4, -324075# CHECK-INSTR: cv.cmplt.sci.h t3, t4, -324076# CHECK-ENCODING: [0x7b,0xee,0x0e,0x25]4077# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4078 4079cv.cmplt.sci.h a0, a1, 74080# CHECK-INSTR: cv.cmplt.sci.h a0, a1, 74081# CHECK-ENCODING: [0x7b,0xe5,0x35,0x26]4082# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4083 4084cv.cmplt.sci.h s0, s1, -14085# CHECK-INSTR: cv.cmplt.sci.h s0, s1, -14086# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x27]4087# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4088 4089//===----------------------------------------------------------------------===//4090// cv.cmplt.sci.b4091//===----------------------------------------------------------------------===//4092 4093cv.cmplt.sci.b t0, t1, 04094# CHECK-INSTR: cv.cmplt.sci.b t0, t1, 04095# CHECK-ENCODING: [0xfb,0x72,0x03,0x24]4096# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4097 4098cv.cmplt.sci.b t3, t4, -324099# CHECK-INSTR: cv.cmplt.sci.b t3, t4, -324100# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x25]4101# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4102 4103cv.cmplt.sci.b a0, a1, 74104# CHECK-INSTR: cv.cmplt.sci.b a0, a1, 74105# CHECK-ENCODING: [0x7b,0xf5,0x35,0x26]4106# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4107 4108cv.cmplt.sci.b s0, s1, -14109# CHECK-INSTR: cv.cmplt.sci.b s0, s1, -14110# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x27]4111# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4112 4113//===----------------------------------------------------------------------===//4114// cv.cmple.h4115//===----------------------------------------------------------------------===//4116 4117cv.cmple.h t0, t1, t24118# CHECK-INSTR: cv.cmple.h t0, t1, t24119# CHECK-ENCODING: [0xfb,0x02,0x73,0x2c]4120# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4121 4122cv.cmple.h t3, t4, t54123# CHECK-INSTR: cv.cmple.h t3, t4, t54124# CHECK-ENCODING: [0x7b,0x8e,0xee,0x2d]4125# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4126 4127cv.cmple.h a0, a1, a24128# CHECK-INSTR: cv.cmple.h a0, a1, a24129# CHECK-ENCODING: [0x7b,0x85,0xc5,0x2c]4130# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4131 4132cv.cmple.h s0, s1, s24133# CHECK-INSTR: cv.cmple.h s0, s1, s24134# CHECK-ENCODING: [0x7b,0x84,0x24,0x2d]4135# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4136 4137//===----------------------------------------------------------------------===//4138// cv.cmple.b4139//===----------------------------------------------------------------------===//4140 4141cv.cmple.b t0, t1, t24142# CHECK-INSTR: cv.cmple.b t0, t1, t24143# CHECK-ENCODING: [0xfb,0x12,0x73,0x2c]4144# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4145 4146cv.cmple.b t3, t4, t54147# CHECK-INSTR: cv.cmple.b t3, t4, t54148# CHECK-ENCODING: [0x7b,0x9e,0xee,0x2d]4149# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4150 4151cv.cmple.b a0, a1, a24152# CHECK-INSTR: cv.cmple.b a0, a1, a24153# CHECK-ENCODING: [0x7b,0x95,0xc5,0x2c]4154# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4155 4156cv.cmple.b s0, s1, s24157# CHECK-INSTR: cv.cmple.b s0, s1, s24158# CHECK-ENCODING: [0x7b,0x94,0x24,0x2d]4159# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4160 4161//===----------------------------------------------------------------------===//4162// cv.cmple.sc.h4163//===----------------------------------------------------------------------===//4164 4165cv.cmple.sc.h t0, t1, t24166# CHECK-INSTR: cv.cmple.sc.h t0, t1, t24167# CHECK-ENCODING: [0xfb,0x42,0x73,0x2c]4168# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4169 4170cv.cmple.sc.h t3, t4, t54171# CHECK-INSTR: cv.cmple.sc.h t3, t4, t54172# CHECK-ENCODING: [0x7b,0xce,0xee,0x2d]4173# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4174 4175cv.cmple.sc.h a0, a1, a24176# CHECK-INSTR: cv.cmple.sc.h a0, a1, a24177# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x2c]4178# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4179 4180cv.cmple.sc.h s0, s1, s24181# CHECK-INSTR: cv.cmple.sc.h s0, s1, s24182# CHECK-ENCODING: [0x7b,0xc4,0x24,0x2d]4183# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4184 4185//===----------------------------------------------------------------------===//4186// cv.cmple.sc.b4187//===----------------------------------------------------------------------===//4188 4189cv.cmple.sc.b t0, t1, t24190# CHECK-INSTR: cv.cmple.sc.b t0, t1, t24191# CHECK-ENCODING: [0xfb,0x52,0x73,0x2c]4192# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4193 4194cv.cmple.sc.b t3, t4, t54195# CHECK-INSTR: cv.cmple.sc.b t3, t4, t54196# CHECK-ENCODING: [0x7b,0xde,0xee,0x2d]4197# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4198 4199cv.cmple.sc.b a0, a1, a24200# CHECK-INSTR: cv.cmple.sc.b a0, a1, a24201# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x2c]4202# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4203 4204cv.cmple.sc.b s0, s1, s24205# CHECK-INSTR: cv.cmple.sc.b s0, s1, s24206# CHECK-ENCODING: [0x7b,0xd4,0x24,0x2d]4207# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4208 4209//===----------------------------------------------------------------------===//4210// cv.cmple.sci.h4211//===----------------------------------------------------------------------===//4212 4213cv.cmple.sci.h t0, t1, 04214# CHECK-INSTR: cv.cmple.sci.h t0, t1, 04215# CHECK-ENCODING: [0xfb,0x62,0x03,0x2c]4216# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4217 4218cv.cmple.sci.h t3, t4, -324219# CHECK-INSTR: cv.cmple.sci.h t3, t4, -324220# CHECK-ENCODING: [0x7b,0xee,0x0e,0x2d]4221# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4222 4223cv.cmple.sci.h a0, a1, 74224# CHECK-INSTR: cv.cmple.sci.h a0, a1, 74225# CHECK-ENCODING: [0x7b,0xe5,0x35,0x2e]4226# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4227 4228cv.cmple.sci.h s0, s1, -14229# CHECK-INSTR: cv.cmple.sci.h s0, s1, -14230# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x2f]4231# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4232 4233//===----------------------------------------------------------------------===//4234// cv.cmple.sci.b4235//===----------------------------------------------------------------------===//4236 4237cv.cmple.sci.b t0, t1, 04238# CHECK-INSTR: cv.cmple.sci.b t0, t1, 04239# CHECK-ENCODING: [0xfb,0x72,0x03,0x2c]4240# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4241 4242cv.cmple.sci.b t3, t4, -324243# CHECK-INSTR: cv.cmple.sci.b t3, t4, -324244# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x2d]4245# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4246 4247cv.cmple.sci.b a0, a1, 74248# CHECK-INSTR: cv.cmple.sci.b a0, a1, 74249# CHECK-ENCODING: [0x7b,0xf5,0x35,0x2e]4250# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4251 4252cv.cmple.sci.b s0, s1, -14253# CHECK-INSTR: cv.cmple.sci.b s0, s1, -14254# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x2f]4255# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4256 4257//===----------------------------------------------------------------------===//4258// cv.cmpgtu.h4259//===----------------------------------------------------------------------===//4260 4261cv.cmpgtu.h t0, t1, t24262# CHECK-INSTR: cv.cmpgtu.h t0, t1, t24263# CHECK-ENCODING: [0xfb,0x02,0x73,0x34]4264# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4265 4266cv.cmpgtu.h t3, t4, t54267# CHECK-INSTR: cv.cmpgtu.h t3, t4, t54268# CHECK-ENCODING: [0x7b,0x8e,0xee,0x35]4269# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4270 4271cv.cmpgtu.h a0, a1, a24272# CHECK-INSTR: cv.cmpgtu.h a0, a1, a24273# CHECK-ENCODING: [0x7b,0x85,0xc5,0x34]4274# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4275 4276cv.cmpgtu.h s0, s1, s24277# CHECK-INSTR: cv.cmpgtu.h s0, s1, s24278# CHECK-ENCODING: [0x7b,0x84,0x24,0x35]4279# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4280 4281//===----------------------------------------------------------------------===//4282// cv.cmpgtu.b4283//===----------------------------------------------------------------------===//4284 4285cv.cmpgtu.b t0, t1, t24286# CHECK-INSTR: cv.cmpgtu.b t0, t1, t24287# CHECK-ENCODING: [0xfb,0x12,0x73,0x34]4288# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4289 4290cv.cmpgtu.b t3, t4, t54291# CHECK-INSTR: cv.cmpgtu.b t3, t4, t54292# CHECK-ENCODING: [0x7b,0x9e,0xee,0x35]4293# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4294 4295cv.cmpgtu.b a0, a1, a24296# CHECK-INSTR: cv.cmpgtu.b a0, a1, a24297# CHECK-ENCODING: [0x7b,0x95,0xc5,0x34]4298# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4299 4300cv.cmpgtu.b s0, s1, s24301# CHECK-INSTR: cv.cmpgtu.b s0, s1, s24302# CHECK-ENCODING: [0x7b,0x94,0x24,0x35]4303# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4304 4305//===----------------------------------------------------------------------===//4306// cv.cmpgtu.sc.h4307//===----------------------------------------------------------------------===//4308 4309cv.cmpgtu.sc.h t0, t1, t24310# CHECK-INSTR: cv.cmpgtu.sc.h t0, t1, t24311# CHECK-ENCODING: [0xfb,0x42,0x73,0x34]4312# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4313 4314cv.cmpgtu.sc.h t3, t4, t54315# CHECK-INSTR: cv.cmpgtu.sc.h t3, t4, t54316# CHECK-ENCODING: [0x7b,0xce,0xee,0x35]4317# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4318 4319cv.cmpgtu.sc.h a0, a1, a24320# CHECK-INSTR: cv.cmpgtu.sc.h a0, a1, a24321# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x34]4322# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4323 4324cv.cmpgtu.sc.h s0, s1, s24325# CHECK-INSTR: cv.cmpgtu.sc.h s0, s1, s24326# CHECK-ENCODING: [0x7b,0xc4,0x24,0x35]4327# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4328 4329//===----------------------------------------------------------------------===//4330// cv.cmpgtu.sc.b4331//===----------------------------------------------------------------------===//4332 4333cv.cmpgtu.sc.b t0, t1, t24334# CHECK-INSTR: cv.cmpgtu.sc.b t0, t1, t24335# CHECK-ENCODING: [0xfb,0x52,0x73,0x34]4336# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4337 4338cv.cmpgtu.sc.b t3, t4, t54339# CHECK-INSTR: cv.cmpgtu.sc.b t3, t4, t54340# CHECK-ENCODING: [0x7b,0xde,0xee,0x35]4341# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4342 4343cv.cmpgtu.sc.b a0, a1, a24344# CHECK-INSTR: cv.cmpgtu.sc.b a0, a1, a24345# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x34]4346# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4347 4348cv.cmpgtu.sc.b s0, s1, s24349# CHECK-INSTR: cv.cmpgtu.sc.b s0, s1, s24350# CHECK-ENCODING: [0x7b,0xd4,0x24,0x35]4351# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4352 4353//===----------------------------------------------------------------------===//4354// cv.cmpgtu.sci.h4355//===----------------------------------------------------------------------===//4356 4357cv.cmpgtu.sci.h t0, t1, 04358# CHECK-INSTR: cv.cmpgtu.sci.h t0, t1, 04359# CHECK-ENCODING: [0xfb,0x62,0x03,0x34]4360# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4361 4362cv.cmpgtu.sci.h t3, t4, 324363# CHECK-INSTR: cv.cmpgtu.sci.h t3, t4, 324364# CHECK-ENCODING: [0x7b,0xee,0x0e,0x35]4365# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4366 4367cv.cmpgtu.sci.h a0, a1, 74368# CHECK-INSTR: cv.cmpgtu.sci.h a0, a1, 74369# CHECK-ENCODING: [0x7b,0xe5,0x35,0x36]4370# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4371 4372cv.cmpgtu.sci.h s0, s1, 634373# CHECK-INSTR: cv.cmpgtu.sci.h s0, s1, 634374# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x37]4375# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4376 4377//===----------------------------------------------------------------------===//4378// cv.cmpgtu.sci.b4379//===----------------------------------------------------------------------===//4380 4381cv.cmpgtu.sci.b t0, t1, 04382# CHECK-INSTR: cv.cmpgtu.sci.b t0, t1, 04383# CHECK-ENCODING: [0xfb,0x72,0x03,0x34]4384# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4385 4386cv.cmpgtu.sci.b t3, t4, 324387# CHECK-INSTR: cv.cmpgtu.sci.b t3, t4, 324388# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x35]4389# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4390 4391cv.cmpgtu.sci.b a0, a1, 74392# CHECK-INSTR: cv.cmpgtu.sci.b a0, a1, 74393# CHECK-ENCODING: [0x7b,0xf5,0x35,0x36]4394# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4395 4396cv.cmpgtu.sci.b s0, s1, 634397# CHECK-INSTR: cv.cmpgtu.sci.b s0, s1, 634398# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x37]4399# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4400 4401//===----------------------------------------------------------------------===//4402// cv.cmpgeu.h4403//===----------------------------------------------------------------------===//4404 4405cv.cmpgeu.h t0, t1, t24406# CHECK-INSTR: cv.cmpgeu.h t0, t1, t24407# CHECK-ENCODING: [0xfb,0x02,0x73,0x3c]4408# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4409 4410cv.cmpgeu.h t3, t4, t54411# CHECK-INSTR: cv.cmpgeu.h t3, t4, t54412# CHECK-ENCODING: [0x7b,0x8e,0xee,0x3d]4413# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4414 4415cv.cmpgeu.h a0, a1, a24416# CHECK-INSTR: cv.cmpgeu.h a0, a1, a24417# CHECK-ENCODING: [0x7b,0x85,0xc5,0x3c]4418# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4419 4420cv.cmpgeu.h s0, s1, s24421# CHECK-INSTR: cv.cmpgeu.h s0, s1, s24422# CHECK-ENCODING: [0x7b,0x84,0x24,0x3d]4423# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4424 4425//===----------------------------------------------------------------------===//4426// cv.cmpgeu.b4427//===----------------------------------------------------------------------===//4428 4429cv.cmpgeu.b t0, t1, t24430# CHECK-INSTR: cv.cmpgeu.b t0, t1, t24431# CHECK-ENCODING: [0xfb,0x12,0x73,0x3c]4432# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4433 4434cv.cmpgeu.b t3, t4, t54435# CHECK-INSTR: cv.cmpgeu.b t3, t4, t54436# CHECK-ENCODING: [0x7b,0x9e,0xee,0x3d]4437# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4438 4439cv.cmpgeu.b a0, a1, a24440# CHECK-INSTR: cv.cmpgeu.b a0, a1, a24441# CHECK-ENCODING: [0x7b,0x95,0xc5,0x3c]4442# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4443 4444cv.cmpgeu.b s0, s1, s24445# CHECK-INSTR: cv.cmpgeu.b s0, s1, s24446# CHECK-ENCODING: [0x7b,0x94,0x24,0x3d]4447# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4448 4449//===----------------------------------------------------------------------===//4450// cv.cmpgeu.sc.h4451//===----------------------------------------------------------------------===//4452 4453cv.cmpgeu.sc.h t0, t1, t24454# CHECK-INSTR: cv.cmpgeu.sc.h t0, t1, t24455# CHECK-ENCODING: [0xfb,0x42,0x73,0x3c]4456# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4457 4458cv.cmpgeu.sc.h t3, t4, t54459# CHECK-INSTR: cv.cmpgeu.sc.h t3, t4, t54460# CHECK-ENCODING: [0x7b,0xce,0xee,0x3d]4461# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4462 4463cv.cmpgeu.sc.h a0, a1, a24464# CHECK-INSTR: cv.cmpgeu.sc.h a0, a1, a24465# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x3c]4466# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4467 4468cv.cmpgeu.sc.h s0, s1, s24469# CHECK-INSTR: cv.cmpgeu.sc.h s0, s1, s24470# CHECK-ENCODING: [0x7b,0xc4,0x24,0x3d]4471# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4472 4473//===----------------------------------------------------------------------===//4474// cv.cmpgeu.sc.b4475//===----------------------------------------------------------------------===//4476 4477cv.cmpgeu.sc.b t0, t1, t24478# CHECK-INSTR: cv.cmpgeu.sc.b t0, t1, t24479# CHECK-ENCODING: [0xfb,0x52,0x73,0x3c]4480# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4481 4482cv.cmpgeu.sc.b t3, t4, t54483# CHECK-INSTR: cv.cmpgeu.sc.b t3, t4, t54484# CHECK-ENCODING: [0x7b,0xde,0xee,0x3d]4485# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4486 4487cv.cmpgeu.sc.b a0, a1, a24488# CHECK-INSTR: cv.cmpgeu.sc.b a0, a1, a24489# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x3c]4490# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4491 4492cv.cmpgeu.sc.b s0, s1, s24493# CHECK-INSTR: cv.cmpgeu.sc.b s0, s1, s24494# CHECK-ENCODING: [0x7b,0xd4,0x24,0x3d]4495# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4496 4497//===----------------------------------------------------------------------===//4498// cv.cmpgeu.sci.h4499//===----------------------------------------------------------------------===//4500 4501cv.cmpgeu.sci.h t0, t1, 04502# CHECK-INSTR: cv.cmpgeu.sci.h t0, t1, 04503# CHECK-ENCODING: [0xfb,0x62,0x03,0x3c]4504# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4505 4506cv.cmpgeu.sci.h t3, t4, 324507# CHECK-INSTR: cv.cmpgeu.sci.h t3, t4, 324508# CHECK-ENCODING: [0x7b,0xee,0x0e,0x3d]4509# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4510 4511cv.cmpgeu.sci.h a0, a1, 74512# CHECK-INSTR: cv.cmpgeu.sci.h a0, a1, 74513# CHECK-ENCODING: [0x7b,0xe5,0x35,0x3e]4514# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4515 4516cv.cmpgeu.sci.h s0, s1, 634517# CHECK-INSTR: cv.cmpgeu.sci.h s0, s1, 634518# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x3f]4519# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4520 4521//===----------------------------------------------------------------------===//4522// cv.cmpgeu.sci.b4523//===----------------------------------------------------------------------===//4524 4525cv.cmpgeu.sci.b t0, t1, 04526# CHECK-INSTR: cv.cmpgeu.sci.b t0, t1, 04527# CHECK-ENCODING: [0xfb,0x72,0x03,0x3c]4528# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4529 4530cv.cmpgeu.sci.b t3, t4, 324531# CHECK-INSTR: cv.cmpgeu.sci.b t3, t4, 324532# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x3d]4533# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4534 4535cv.cmpgeu.sci.b a0, a1, 74536# CHECK-INSTR: cv.cmpgeu.sci.b a0, a1, 74537# CHECK-ENCODING: [0x7b,0xf5,0x35,0x3e]4538# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4539 4540cv.cmpgeu.sci.b s0, s1, 634541# CHECK-INSTR: cv.cmpgeu.sci.b s0, s1, 634542# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x3f]4543# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4544 4545//===----------------------------------------------------------------------===//4546// cv.cmpltu.h4547//===----------------------------------------------------------------------===//4548 4549cv.cmpltu.h t0, t1, t24550# CHECK-INSTR: cv.cmpltu.h t0, t1, t24551# CHECK-ENCODING: [0xfb,0x02,0x73,0x44]4552# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4553 4554cv.cmpltu.h t3, t4, t54555# CHECK-INSTR: cv.cmpltu.h t3, t4, t54556# CHECK-ENCODING: [0x7b,0x8e,0xee,0x45]4557# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4558 4559cv.cmpltu.h a0, a1, a24560# CHECK-INSTR: cv.cmpltu.h a0, a1, a24561# CHECK-ENCODING: [0x7b,0x85,0xc5,0x44]4562# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4563 4564cv.cmpltu.h s0, s1, s24565# CHECK-INSTR: cv.cmpltu.h s0, s1, s24566# CHECK-ENCODING: [0x7b,0x84,0x24,0x45]4567# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4568 4569//===----------------------------------------------------------------------===//4570// cv.cmpltu.b4571//===----------------------------------------------------------------------===//4572 4573cv.cmpltu.b t0, t1, t24574# CHECK-INSTR: cv.cmpltu.b t0, t1, t24575# CHECK-ENCODING: [0xfb,0x12,0x73,0x44]4576# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4577 4578cv.cmpltu.b t3, t4, t54579# CHECK-INSTR: cv.cmpltu.b t3, t4, t54580# CHECK-ENCODING: [0x7b,0x9e,0xee,0x45]4581# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4582 4583cv.cmpltu.b a0, a1, a24584# CHECK-INSTR: cv.cmpltu.b a0, a1, a24585# CHECK-ENCODING: [0x7b,0x95,0xc5,0x44]4586# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4587 4588cv.cmpltu.b s0, s1, s24589# CHECK-INSTR: cv.cmpltu.b s0, s1, s24590# CHECK-ENCODING: [0x7b,0x94,0x24,0x45]4591# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4592 4593//===----------------------------------------------------------------------===//4594// cv.cmpltu.sc.h4595//===----------------------------------------------------------------------===//4596 4597cv.cmpltu.sc.h t0, t1, t24598# CHECK-INSTR: cv.cmpltu.sc.h t0, t1, t24599# CHECK-ENCODING: [0xfb,0x42,0x73,0x44]4600# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4601 4602cv.cmpltu.sc.h t3, t4, t54603# CHECK-INSTR: cv.cmpltu.sc.h t3, t4, t54604# CHECK-ENCODING: [0x7b,0xce,0xee,0x45]4605# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4606 4607cv.cmpltu.sc.h a0, a1, a24608# CHECK-INSTR: cv.cmpltu.sc.h a0, a1, a24609# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x44]4610# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4611 4612cv.cmpltu.sc.h s0, s1, s24613# CHECK-INSTR: cv.cmpltu.sc.h s0, s1, s24614# CHECK-ENCODING: [0x7b,0xc4,0x24,0x45]4615# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4616 4617//===----------------------------------------------------------------------===//4618// cv.cmpltu.sc.b4619//===----------------------------------------------------------------------===//4620 4621cv.cmpltu.sc.b t0, t1, t24622# CHECK-INSTR: cv.cmpltu.sc.b t0, t1, t24623# CHECK-ENCODING: [0xfb,0x52,0x73,0x44]4624# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4625 4626cv.cmpltu.sc.b t3, t4, t54627# CHECK-INSTR: cv.cmpltu.sc.b t3, t4, t54628# CHECK-ENCODING: [0x7b,0xde,0xee,0x45]4629# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4630 4631cv.cmpltu.sc.b a0, a1, a24632# CHECK-INSTR: cv.cmpltu.sc.b a0, a1, a24633# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x44]4634# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4635 4636cv.cmpltu.sc.b s0, s1, s24637# CHECK-INSTR: cv.cmpltu.sc.b s0, s1, s24638# CHECK-ENCODING: [0x7b,0xd4,0x24,0x45]4639# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4640 4641//===----------------------------------------------------------------------===//4642// cv.cmpltu.sci.h4643//===----------------------------------------------------------------------===//4644 4645cv.cmpltu.sci.h t0, t1, 04646# CHECK-INSTR: cv.cmpltu.sci.h t0, t1, 04647# CHECK-ENCODING: [0xfb,0x62,0x03,0x44]4648# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4649 4650cv.cmpltu.sci.h t3, t4, 324651# CHECK-INSTR: cv.cmpltu.sci.h t3, t4, 324652# CHECK-ENCODING: [0x7b,0xee,0x0e,0x45]4653# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4654 4655cv.cmpltu.sci.h a0, a1, 74656# CHECK-INSTR: cv.cmpltu.sci.h a0, a1, 74657# CHECK-ENCODING: [0x7b,0xe5,0x35,0x46]4658# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4659 4660cv.cmpltu.sci.h s0, s1, 634661# CHECK-INSTR: cv.cmpltu.sci.h s0, s1, 634662# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x47]4663# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4664 4665//===----------------------------------------------------------------------===//4666// cv.cmpltu.sci.b4667//===----------------------------------------------------------------------===//4668 4669cv.cmpltu.sci.b t0, t1, 04670# CHECK-INSTR: cv.cmpltu.sci.b t0, t1, 04671# CHECK-ENCODING: [0xfb,0x72,0x03,0x44]4672# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4673 4674cv.cmpltu.sci.b t3, t4, 324675# CHECK-INSTR: cv.cmpltu.sci.b t3, t4, 324676# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x45]4677# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4678 4679cv.cmpltu.sci.b a0, a1, 74680# CHECK-INSTR: cv.cmpltu.sci.b a0, a1, 74681# CHECK-ENCODING: [0x7b,0xf5,0x35,0x46]4682# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4683 4684cv.cmpltu.sci.b s0, s1, 634685# CHECK-INSTR: cv.cmpltu.sci.b s0, s1, 634686# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x47]4687# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4688 4689//===----------------------------------------------------------------------===//4690// cv.cmpleu.h4691//===----------------------------------------------------------------------===//4692 4693cv.cmpleu.h t0, t1, t24694# CHECK-INSTR: cv.cmpleu.h t0, t1, t24695# CHECK-ENCODING: [0xfb,0x02,0x73,0x4c]4696# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4697 4698cv.cmpleu.h t3, t4, t54699# CHECK-INSTR: cv.cmpleu.h t3, t4, t54700# CHECK-ENCODING: [0x7b,0x8e,0xee,0x4d]4701# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4702 4703cv.cmpleu.h a0, a1, a24704# CHECK-INSTR: cv.cmpleu.h a0, a1, a24705# CHECK-ENCODING: [0x7b,0x85,0xc5,0x4c]4706# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4707 4708cv.cmpleu.h s0, s1, s24709# CHECK-INSTR: cv.cmpleu.h s0, s1, s24710# CHECK-ENCODING: [0x7b,0x84,0x24,0x4d]4711# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4712 4713//===----------------------------------------------------------------------===//4714// cv.cmpleu.b4715//===----------------------------------------------------------------------===//4716 4717cv.cmpleu.b t0, t1, t24718# CHECK-INSTR: cv.cmpleu.b t0, t1, t24719# CHECK-ENCODING: [0xfb,0x12,0x73,0x4c]4720# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4721 4722cv.cmpleu.b t3, t4, t54723# CHECK-INSTR: cv.cmpleu.b t3, t4, t54724# CHECK-ENCODING: [0x7b,0x9e,0xee,0x4d]4725# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4726 4727cv.cmpleu.b a0, a1, a24728# CHECK-INSTR: cv.cmpleu.b a0, a1, a24729# CHECK-ENCODING: [0x7b,0x95,0xc5,0x4c]4730# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4731 4732cv.cmpleu.b s0, s1, s24733# CHECK-INSTR: cv.cmpleu.b s0, s1, s24734# CHECK-ENCODING: [0x7b,0x94,0x24,0x4d]4735# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4736 4737//===----------------------------------------------------------------------===//4738// cv.cmpleu.sc.h4739//===----------------------------------------------------------------------===//4740 4741cv.cmpleu.sc.h t0, t1, t24742# CHECK-INSTR: cv.cmpleu.sc.h t0, t1, t24743# CHECK-ENCODING: [0xfb,0x42,0x73,0x4c]4744# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4745 4746cv.cmpleu.sc.h t3, t4, t54747# CHECK-INSTR: cv.cmpleu.sc.h t3, t4, t54748# CHECK-ENCODING: [0x7b,0xce,0xee,0x4d]4749# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4750 4751cv.cmpleu.sc.h a0, a1, a24752# CHECK-INSTR: cv.cmpleu.sc.h a0, a1, a24753# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x4c]4754# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4755 4756cv.cmpleu.sc.h s0, s1, s24757# CHECK-INSTR: cv.cmpleu.sc.h s0, s1, s24758# CHECK-ENCODING: [0x7b,0xc4,0x24,0x4d]4759# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4760 4761//===----------------------------------------------------------------------===//4762// cv.cmpleu.sc.b4763//===----------------------------------------------------------------------===//4764 4765cv.cmpleu.sc.b t0, t1, t24766# CHECK-INSTR: cv.cmpleu.sc.b t0, t1, t24767# CHECK-ENCODING: [0xfb,0x52,0x73,0x4c]4768# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4769 4770cv.cmpleu.sc.b t3, t4, t54771# CHECK-INSTR: cv.cmpleu.sc.b t3, t4, t54772# CHECK-ENCODING: [0x7b,0xde,0xee,0x4d]4773# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4774 4775cv.cmpleu.sc.b a0, a1, a24776# CHECK-INSTR: cv.cmpleu.sc.b a0, a1, a24777# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x4c]4778# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4779 4780cv.cmpleu.sc.b s0, s1, s24781# CHECK-INSTR: cv.cmpleu.sc.b s0, s1, s24782# CHECK-ENCODING: [0x7b,0xd4,0x24,0x4d]4783# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4784 4785//===----------------------------------------------------------------------===//4786// cv.cmpleu.sci.h4787//===----------------------------------------------------------------------===//4788 4789cv.cmpleu.sci.h t0, t1, 04790# CHECK-INSTR: cv.cmpleu.sci.h t0, t1, 04791# CHECK-ENCODING: [0xfb,0x62,0x03,0x4c]4792# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4793 4794cv.cmpleu.sci.h t3, t4, 324795# CHECK-INSTR: cv.cmpleu.sci.h t3, t4, 324796# CHECK-ENCODING: [0x7b,0xee,0x0e,0x4d]4797# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4798 4799cv.cmpleu.sci.h a0, a1, 74800# CHECK-INSTR: cv.cmpleu.sci.h a0, a1, 74801# CHECK-ENCODING: [0x7b,0xe5,0x35,0x4e]4802# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4803 4804cv.cmpleu.sci.h s0, s1, 634805# CHECK-INSTR: cv.cmpleu.sci.h s0, s1, 634806# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x4f]4807# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4808 4809//===----------------------------------------------------------------------===//4810// cv.cmpleu.sci.b4811//===----------------------------------------------------------------------===//4812 4813cv.cmpleu.sci.b t0, t1, 04814# CHECK-INSTR: cv.cmpleu.sci.b t0, t1, 04815# CHECK-ENCODING: [0xfb,0x72,0x03,0x4c]4816# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4817 4818cv.cmpleu.sci.b t3, t4, 324819# CHECK-INSTR: cv.cmpleu.sci.b t3, t4, 324820# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x4d]4821# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4822 4823cv.cmpleu.sci.b a0, a1, 74824# CHECK-INSTR: cv.cmpleu.sci.b a0, a1, 74825# CHECK-ENCODING: [0x7b,0xf5,0x35,0x4e]4826# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4827 4828cv.cmpleu.sci.b s0, s1, 634829# CHECK-INSTR: cv.cmpleu.sci.b s0, s1, 634830# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x4f]4831# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4832 4833//===----------------------------------------------------------------------===//4834// cv.cplxmul.r4835//===----------------------------------------------------------------------===//4836 4837cv.cplxmul.r t0, t1, t24838# CHECK-INSTR: cv.cplxmul.r t0, t1, t24839# CHECK-ENCODING: [0xfb,0x02,0x73,0x54]4840# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4841 4842cv.cplxmul.r t3, t4, t54843# CHECK-INSTR: cv.cplxmul.r t3, t4, t54844# CHECK-ENCODING: [0x7b,0x8e,0xee,0x55]4845# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4846 4847cv.cplxmul.r a0, a1, a24848# CHECK-INSTR: cv.cplxmul.r a0, a1, a24849# CHECK-ENCODING: [0x7b,0x85,0xc5,0x54]4850# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4851 4852cv.cplxmul.r s0, s1, s24853# CHECK-INSTR: cv.cplxmul.r s0, s1, s24854# CHECK-ENCODING: [0x7b,0x84,0x24,0x55]4855# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4856 4857//===----------------------------------------------------------------------===//4858// cv.cplxmul.i4859//===----------------------------------------------------------------------===//4860 4861cv.cplxmul.i t0, t1, t24862# CHECK-INSTR: cv.cplxmul.i t0, t1, t24863# CHECK-ENCODING: [0xfb,0x02,0x73,0x56]4864# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4865 4866cv.cplxmul.i t3, t4, t54867# CHECK-INSTR: cv.cplxmul.i t3, t4, t54868# CHECK-ENCODING: [0x7b,0x8e,0xee,0x57]4869# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4870 4871cv.cplxmul.i a0, a1, a24872# CHECK-INSTR: cv.cplxmul.i a0, a1, a24873# CHECK-ENCODING: [0x7b,0x85,0xc5,0x56]4874# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4875 4876cv.cplxmul.i s0, s1, s24877# CHECK-INSTR: cv.cplxmul.i s0, s1, s24878# CHECK-ENCODING: [0x7b,0x84,0x24,0x57]4879# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4880 4881//===----------------------------------------------------------------------===//4882// cv.cplxmul.r.div24883//===----------------------------------------------------------------------===//4884 4885cv.cplxmul.r.div2 t0, t1, t24886# CHECK-INSTR: cv.cplxmul.r.div2 t0, t1, t24887# CHECK-ENCODING: [0xfb,0x22,0x73,0x54]4888# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4889 4890cv.cplxmul.r.div2 t3, t4, t54891# CHECK-INSTR: cv.cplxmul.r.div2 t3, t4, t54892# CHECK-ENCODING: [0x7b,0xae,0xee,0x55]4893# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4894 4895cv.cplxmul.r.div2 a0, a1, a24896# CHECK-INSTR: cv.cplxmul.r.div2 a0, a1, a24897# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x54]4898# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4899 4900cv.cplxmul.r.div2 s0, s1, s24901# CHECK-INSTR: cv.cplxmul.r.div2 s0, s1, s24902# CHECK-ENCODING: [0x7b,0xa4,0x24,0x55]4903# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4904 4905//===----------------------------------------------------------------------===//4906// cv.cplxmul.i.div24907//===----------------------------------------------------------------------===//4908 4909cv.cplxmul.i.div2 t0, t1, t24910# CHECK-INSTR: cv.cplxmul.i.div2 t0, t1, t24911# CHECK-ENCODING: [0xfb,0x22,0x73,0x56]4912# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4913 4914cv.cplxmul.i.div2 t3, t4, t54915# CHECK-INSTR: cv.cplxmul.i.div2 t3, t4, t54916# CHECK-ENCODING: [0x7b,0xae,0xee,0x57]4917# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4918 4919cv.cplxmul.i.div2 a0, a1, a24920# CHECK-INSTR: cv.cplxmul.i.div2 a0, a1, a24921# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x56]4922# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4923 4924cv.cplxmul.i.div2 s0, s1, s24925# CHECK-INSTR: cv.cplxmul.i.div2 s0, s1, s24926# CHECK-ENCODING: [0x7b,0xa4,0x24,0x57]4927# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4928 4929//===----------------------------------------------------------------------===//4930// cv.cplxmul.r.div44931//===----------------------------------------------------------------------===//4932 4933cv.cplxmul.r.div4 t0, t1, t24934# CHECK-INSTR: cv.cplxmul.r.div4 t0, t1, t24935# CHECK-ENCODING: [0xfb,0x42,0x73,0x54]4936# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4937 4938cv.cplxmul.r.div4 t3, t4, t54939# CHECK-INSTR: cv.cplxmul.r.div4 t3, t4, t54940# CHECK-ENCODING: [0x7b,0xce,0xee,0x55]4941# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4942 4943cv.cplxmul.r.div4 a0, a1, a24944# CHECK-INSTR: cv.cplxmul.r.div4 a0, a1, a24945# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x54]4946# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4947 4948cv.cplxmul.r.div4 s0, s1, s24949# CHECK-INSTR: cv.cplxmul.r.div4 s0, s1, s24950# CHECK-ENCODING: [0x7b,0xc4,0x24,0x55]4951# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4952 4953//===----------------------------------------------------------------------===//4954// cv.cplxmul.i.div44955//===----------------------------------------------------------------------===//4956 4957cv.cplxmul.i.div4 t0, t1, t24958# CHECK-INSTR: cv.cplxmul.i.div4 t0, t1, t24959# CHECK-ENCODING: [0xfb,0x42,0x73,0x56]4960# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4961 4962cv.cplxmul.i.div4 t3, t4, t54963# CHECK-INSTR: cv.cplxmul.i.div4 t3, t4, t54964# CHECK-ENCODING: [0x7b,0xce,0xee,0x57]4965# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4966 4967cv.cplxmul.i.div4 a0, a1, a24968# CHECK-INSTR: cv.cplxmul.i.div4 a0, a1, a24969# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x56]4970# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4971 4972cv.cplxmul.i.div4 s0, s1, s24973# CHECK-INSTR: cv.cplxmul.i.div4 s0, s1, s24974# CHECK-ENCODING: [0x7b,0xc4,0x24,0x57]4975# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4976 4977//===----------------------------------------------------------------------===//4978// cv.cplxmul.r.div84979//===----------------------------------------------------------------------===//4980 4981cv.cplxmul.r.div8 t0, t1, t24982# CHECK-INSTR: cv.cplxmul.r.div8 t0, t1, t24983# CHECK-ENCODING: [0xfb,0x62,0x73,0x54]4984# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4985 4986cv.cplxmul.r.div8 t3, t4, t54987# CHECK-INSTR: cv.cplxmul.r.div8 t3, t4, t54988# CHECK-ENCODING: [0x7b,0xee,0xee,0x55]4989# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4990 4991cv.cplxmul.r.div8 a0, a1, a24992# CHECK-INSTR: cv.cplxmul.r.div8 a0, a1, a24993# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x54]4994# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}4995 4996cv.cplxmul.r.div8 s0, s1, s24997# CHECK-INSTR: cv.cplxmul.r.div8 s0, s1, s24998# CHECK-ENCODING: [0x7b,0xe4,0x24,0x55]4999# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5000 5001//===----------------------------------------------------------------------===//5002// cv.cplxmul.i.div85003//===----------------------------------------------------------------------===//5004 5005cv.cplxmul.i.div8 t0, t1, t25006# CHECK-INSTR: cv.cplxmul.i.div8 t0, t1, t25007# CHECK-ENCODING: [0xfb,0x62,0x73,0x56]5008# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5009 5010cv.cplxmul.i.div8 t3, t4, t55011# CHECK-INSTR: cv.cplxmul.i.div8 t3, t4, t55012# CHECK-ENCODING: [0x7b,0xee,0xee,0x57]5013# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5014 5015cv.cplxmul.i.div8 a0, a1, a25016# CHECK-INSTR: cv.cplxmul.i.div8 a0, a1, a25017# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x56]5018# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5019 5020cv.cplxmul.i.div8 s0, s1, s25021# CHECK-INSTR: cv.cplxmul.i.div8 s0, s1, s25022# CHECK-ENCODING: [0x7b,0xe4,0x24,0x57]5023# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5024 5025//===----------------------------------------------------------------------===//5026// cv.cplxconj5027//===----------------------------------------------------------------------===//5028 5029cv.cplxconj t0, t15030# CHECK-INSTR: cv.cplxconj t0, t15031# CHECK-ENCODING: [0xfb,0x02,0x03,0x5c]5032# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5033 5034cv.cplxconj t3, t45035# CHECK-INSTR: cv.cplxconj t3, t45036# CHECK-ENCODING: [0x7b,0x8e,0x0e,0x5c]5037# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5038 5039cv.cplxconj a0, a15040# CHECK-INSTR: cv.cplxconj a0, a15041# CHECK-ENCODING: [0x7b,0x85,0x05,0x5c]5042# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5043 5044cv.cplxconj s0, s15045# CHECK-INSTR: cv.cplxconj s0, s15046# CHECK-ENCODING: [0x7b,0x84,0x04,0x5c]5047# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5048 5049//===----------------------------------------------------------------------===//5050// cv.subrotmj5051//===----------------------------------------------------------------------===//5052 5053cv.subrotmj t0, t1, t25054# CHECK-INSTR: cv.subrotmj t0, t1, t25055# CHECK-ENCODING: [0xfb,0x02,0x73,0x64]5056# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5057 5058cv.subrotmj t3, t4, t55059# CHECK-INSTR: cv.subrotmj t3, t4, t55060# CHECK-ENCODING: [0x7b,0x8e,0xee,0x65]5061# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5062 5063cv.subrotmj a0, a1, a25064# CHECK-INSTR: cv.subrotmj a0, a1, a25065# CHECK-ENCODING: [0x7b,0x85,0xc5,0x64]5066# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5067 5068cv.subrotmj s0, s1, s25069# CHECK-INSTR: cv.subrotmj s0, s1, s25070# CHECK-ENCODING: [0x7b,0x84,0x24,0x65]5071# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5072 5073//===----------------------------------------------------------------------===//5074// cv.subrotmj.div25075//===----------------------------------------------------------------------===//5076 5077cv.subrotmj.div2 t0, t1, t25078# CHECK-INSTR: cv.subrotmj.div2 t0, t1, t25079# CHECK-ENCODING: [0xfb,0x22,0x73,0x64]5080# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5081 5082cv.subrotmj.div2 t3, t4, t55083# CHECK-INSTR: cv.subrotmj.div2 t3, t4, t55084# CHECK-ENCODING: [0x7b,0xae,0xee,0x65]5085# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5086 5087cv.subrotmj.div2 a0, a1, a25088# CHECK-INSTR: cv.subrotmj.div2 a0, a1, a25089# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x64]5090# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5091 5092cv.subrotmj.div2 s0, s1, s25093# CHECK-INSTR: cv.subrotmj.div2 s0, s1, s25094# CHECK-ENCODING: [0x7b,0xa4,0x24,0x65]5095# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5096 5097//===----------------------------------------------------------------------===//5098// cv.subrotmj.div45099//===----------------------------------------------------------------------===//5100 5101cv.subrotmj.div4 t0, t1, t25102# CHECK-INSTR: cv.subrotmj.div4 t0, t1, t25103# CHECK-ENCODING: [0xfb,0x42,0x73,0x64]5104# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5105 5106cv.subrotmj.div4 t3, t4, t55107# CHECK-INSTR: cv.subrotmj.div4 t3, t4, t55108# CHECK-ENCODING: [0x7b,0xce,0xee,0x65]5109# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5110 5111cv.subrotmj.div4 a0, a1, a25112# CHECK-INSTR: cv.subrotmj.div4 a0, a1, a25113# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x64]5114# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5115 5116cv.subrotmj.div4 s0, s1, s25117# CHECK-INSTR: cv.subrotmj.div4 s0, s1, s25118# CHECK-ENCODING: [0x7b,0xc4,0x24,0x65]5119# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5120 5121//===----------------------------------------------------------------------===//5122// cv.subrotmj.div85123//===----------------------------------------------------------------------===//5124 5125cv.subrotmj.div8 t0, t1, t25126# CHECK-INSTR: cv.subrotmj.div8 t0, t1, t25127# CHECK-ENCODING: [0xfb,0x62,0x73,0x64]5128# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5129 5130cv.subrotmj.div8 t3, t4, t55131# CHECK-INSTR: cv.subrotmj.div8 t3, t4, t55132# CHECK-ENCODING: [0x7b,0xee,0xee,0x65]5133# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5134 5135cv.subrotmj.div8 a0, a1, a25136# CHECK-INSTR: cv.subrotmj.div8 a0, a1, a25137# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x64]5138# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5139 5140cv.subrotmj.div8 s0, s1, s25141# CHECK-INSTR: cv.subrotmj.div8 s0, s1, s25142# CHECK-ENCODING: [0x7b,0xe4,0x24,0x65]5143# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5144 5145//===----------------------------------------------------------------------===//5146// cv.add.div25147//===----------------------------------------------------------------------===//5148 5149cv.add.div2 t0, t1, t25150# CHECK-INSTR: cv.add.div2 t0, t1, t25151# CHECK-ENCODING: [0xfb,0x22,0x73,0x6c]5152# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5153 5154cv.add.div2 t3, t4, t55155# CHECK-INSTR: cv.add.div2 t3, t4, t55156# CHECK-ENCODING: [0x7b,0xae,0xee,0x6d]5157# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5158 5159cv.add.div2 a0, a1, a25160# CHECK-INSTR: cv.add.div2 a0, a1, a25161# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x6c]5162# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5163 5164cv.add.div2 s0, s1, s25165# CHECK-INSTR: cv.add.div2 s0, s1, s25166# CHECK-ENCODING: [0x7b,0xa4,0x24,0x6d]5167# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5168 5169//===----------------------------------------------------------------------===//5170// cv.add.div45171//===----------------------------------------------------------------------===//5172 5173cv.add.div4 t0, t1, t25174# CHECK-INSTR: cv.add.div4 t0, t1, t25175# CHECK-ENCODING: [0xfb,0x42,0x73,0x6c]5176# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5177 5178cv.add.div4 t3, t4, t55179# CHECK-INSTR: cv.add.div4 t3, t4, t55180# CHECK-ENCODING: [0x7b,0xce,0xee,0x6d]5181# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5182 5183cv.add.div4 a0, a1, a25184# CHECK-INSTR: cv.add.div4 a0, a1, a25185# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x6c]5186# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5187 5188cv.add.div4 s0, s1, s25189# CHECK-INSTR: cv.add.div4 s0, s1, s25190# CHECK-ENCODING: [0x7b,0xc4,0x24,0x6d]5191# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5192 5193//===----------------------------------------------------------------------===//5194// cv.add.div85195//===----------------------------------------------------------------------===//5196 5197cv.add.div8 t0, t1, t25198# CHECK-INSTR: cv.add.div8 t0, t1, t25199# CHECK-ENCODING: [0xfb,0x62,0x73,0x6c]5200# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5201 5202cv.add.div8 t3, t4, t55203# CHECK-INSTR: cv.add.div8 t3, t4, t55204# CHECK-ENCODING: [0x7b,0xee,0xee,0x6d]5205# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5206 5207cv.add.div8 a0, a1, a25208# CHECK-INSTR: cv.add.div8 a0, a1, a25209# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x6c]5210# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5211 5212cv.add.div8 s0, s1, s25213# CHECK-INSTR: cv.add.div8 s0, s1, s25214# CHECK-ENCODING: [0x7b,0xe4,0x24,0x6d]5215# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5216 5217//===----------------------------------------------------------------------===//5218// cv.sub.div25219//===----------------------------------------------------------------------===//5220 5221cv.sub.div2 t0, t1, t25222# CHECK-INSTR: cv.sub.div2 t0, t1, t25223# CHECK-ENCODING: [0xfb,0x22,0x73,0x74]5224# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5225 5226cv.sub.div2 t3, t4, t55227# CHECK-INSTR: cv.sub.div2 t3, t4, t55228# CHECK-ENCODING: [0x7b,0xae,0xee,0x75]5229# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5230 5231cv.sub.div2 a0, a1, a25232# CHECK-INSTR: cv.sub.div2 a0, a1, a25233# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x74]5234# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5235 5236cv.sub.div2 s0, s1, s25237# CHECK-INSTR: cv.sub.div2 s0, s1, s25238# CHECK-ENCODING: [0x7b,0xa4,0x24,0x75]5239# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5240 5241//===----------------------------------------------------------------------===//5242// cv.sub.div45243//===----------------------------------------------------------------------===//5244 5245cv.sub.div4 t0, t1, t25246# CHECK-INSTR: cv.sub.div4 t0, t1, t25247# CHECK-ENCODING: [0xfb,0x42,0x73,0x74]5248# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5249 5250cv.sub.div4 t3, t4, t55251# CHECK-INSTR: cv.sub.div4 t3, t4, t55252# CHECK-ENCODING: [0x7b,0xce,0xee,0x75]5253# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5254 5255cv.sub.div4 a0, a1, a25256# CHECK-INSTR: cv.sub.div4 a0, a1, a25257# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x74]5258# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5259 5260cv.sub.div4 s0, s1, s25261# CHECK-INSTR: cv.sub.div4 s0, s1, s25262# CHECK-ENCODING: [0x7b,0xc4,0x24,0x75]5263# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5264 5265//===----------------------------------------------------------------------===//5266// cv.sub.div85267//===----------------------------------------------------------------------===//5268 5269cv.sub.div8 t0, t1, t25270# CHECK-INSTR: cv.sub.div8 t0, t1, t25271# CHECK-ENCODING: [0xfb,0x62,0x73,0x74]5272# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5273 5274cv.sub.div8 t3, t4, t55275# CHECK-INSTR: cv.sub.div8 t3, t4, t55276# CHECK-ENCODING: [0x7b,0xee,0xee,0x75]5277# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5278 5279cv.sub.div8 a0, a1, a25280# CHECK-INSTR: cv.sub.div8 a0, a1, a25281# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x74]5282# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5283 5284cv.sub.div8 s0, s1, s25285# CHECK-INSTR: cv.sub.div8 s0, s1, s25286# CHECK-ENCODING: [0x7b,0xe4,0x24,0x75]5287# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}}5288 5289