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1# RUN: llvm-mc -triple riscv32 < %s \2# RUN: | FileCheck -check-prefix=CHECK-INST %s3# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \4# RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s5 6# RUN: llvm-mc -triple riscv64 < %s \7# RUN: | FileCheck -check-prefix=CHECK-INST %s8# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \9# RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s10 11# Check .option relax causes R_RISCV_RELAX to be emitted, and .option12# norelax suppresses it. Also check that if .option relax was enabled13# at any point and an instruction may have been relaxed, diff & branch14# relocations are emitted to ensure correct codegen. See15# linker-relaxation.s and fixups-expr.s for behaviour of the relax16# attribute.17 18.L1:19.option norelax20# CHECK-INST: .option norelax21 22# CHECK-INST: call foo23# CHECK-RELOC: R_RISCV_CALL_PLT foo 0x024# CHECK-RELOC-NOT: R_RISCV25call foo26 27.dword .L2-.L128jal zero, .L129beq s1, s1, .L130 31.L2:32.option relax33# CHECK-INST: .option relax34 35# CHECK-INST: call bar36# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT bar 0x037# CHECK-RELOC-NEXT: R_RISCV_RELAX - 0x038call bar39 40.dword .L2-.L141# CHECK-RELOC-NEXT: R_RISCV_JAL42jal zero, .L143# CHECK-RELOC-NEXT: R_RISCV_BRANCH44beq s1, s1, .L145 46.option norelax47# CHECK-INST: .option norelax48 49# CHECK-INST: call baz50# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT baz 0x051# CHECK-RELOC-NOT: R_RISCV_RELAX - 0x052call baz53 54.dword .L2-.L155# CHECK-RELOC-NEXT: R_RISCV_JAL56jal zero, .L157# CHECK-RELOC-NEXT: R_RISCV_BRANCH58beq s1, s1, .L159 601:61# CHECK-RELOC-NEXT: R_RISCV_PCREL_HI20 .L162auipc t1, %pcrel_hi(.L1)63# CHECK-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp064addi t1, t1, %pcrel_lo(1b)65 66# CHECK-RELOC-NOT: .rela.text167.section .text1,"ax"68nop69call .text170