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1# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -M no-aliases -show-encoding \2# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s3# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \4# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \5# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s6#7# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \8# RUN: | FileCheck -check-prefix=CHECK-RV32 %s9#10# RUN: llvm-mc %s -triple=riscv64 -mattr=+zaamo -M no-aliases -show-encoding \11# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s12# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zaamo < %s \13# RUN: | llvm-objdump --mattr=+zaamo -M no-aliases -d -r - \14# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s15#16# RUN: not llvm-mc -triple riscv32 -mattr=+zaamo < %s 2>&1 \17# RUN: | FileCheck -check-prefix=CHECK-RV32 %s18 19# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)20# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]21# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}22amoswap.d a4, ra, (s0)23# CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3)24# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00]25# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}26amoadd.d a1, a2, (a3)27# CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4)28# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20]29# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}30amoxor.d a2, a3, (a4)31# CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5)32# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60]33# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}34amoand.d a3, a4, (a5)35# CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6)36# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40]37# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}38amoor.d a4, a5, (a6)39# CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7)40# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81]41# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}42amomin.d a5, a6, (a7)43# CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5)44# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1]45# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}46amomax.d s7, s6, (s5)47# CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4)48# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1]49# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}50amominu.d s6, s5, (s4)51# CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3)52# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1]53# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}54amomaxu.d s5, s4, (s3)55 56 57# CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0)58# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]59# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}60amoswap.d.aq a4, ra, (s0)61# CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3)62# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04]63# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}64amoadd.d.aq a1, a2, (a3)65# CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4)66# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24]67# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}68amoxor.d.aq a2, a3, (a4)69# CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5)70# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64]71# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}72amoand.d.aq a3, a4, (a5)73# CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6)74# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44]75# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}76amoor.d.aq a4, a5, (a6)77# CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7)78# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85]79# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}80amomin.d.aq a5, a6, (a7)81# CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5)82# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5]83# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}84amomax.d.aq s7, s6, (s5)85# CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4)86# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5]87# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}88amominu.d.aq s6, s5, (s4)89# CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3)90# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5]91# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}92amomaxu.d.aq s5, s4, (s3)93 94# CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0)95# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]96# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}97amoswap.d.rl a4, ra, (s0)98# CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3)99# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02]100# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}101amoadd.d.rl a1, a2, (a3)102# CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4)103# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22]104# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}105amoxor.d.rl a2, a3, (a4)106# CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5)107# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62]108# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}109amoand.d.rl a3, a4, (a5)110# CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6)111# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42]112# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}113amoor.d.rl a4, a5, (a6)114# CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7)115# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83]116# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}117amomin.d.rl a5, a6, (a7)118# CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5)119# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3]120# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}121amomax.d.rl s7, s6, (s5)122# CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4)123# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3]124# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}125amominu.d.rl s6, s5, (s4)126# CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3)127# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3]128# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}129amomaxu.d.rl s5, s4, (s3)130 131# CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0)132# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]133# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}134amoswap.d.aqrl a4, ra, (s0)135# CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3)136# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06]137# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}138amoadd.d.aqrl a1, a2, (a3)139# CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4)140# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26]141# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}142amoxor.d.aqrl a2, a3, (a4)143# CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5)144# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66]145# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}146amoand.d.aqrl a3, a4, (a5)147# CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6)148# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46]149# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}150amoor.d.aqrl a4, a5, (a6)151# CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7)152# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87]153# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}154amomin.d.aqrl a5, a6, (a7)155# CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5)156# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7]157# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}158amomax.d.aqrl s7, s6, (s5)159# CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4)160# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7]161# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}162amominu.d.aqrl s6, s5, (s4)163# CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3)164# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7]165# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}166amomaxu.d.aqrl s5, s4, (s3)167