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1# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -M no-aliases -show-encoding \2# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s3# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \4# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \5# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s6#7# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \8# RUN: | FileCheck -check-prefix=CHECK-RV32 %s9#10# RUN: llvm-mc %s -triple=riscv64 -mattr=+zalrsc -M no-aliases -show-encoding \11# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s12# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zalrsc < %s \13# RUN: | llvm-objdump --mattr=+zalrsc -M no-aliases -d -r - \14# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s15#16# RUN: not llvm-mc -triple riscv32 -mattr=+zalrsc < %s 2>&1 \17# RUN: | FileCheck -check-prefix=CHECK-RV32 %s18 19# CHECK-ASM-AND-OBJ: lr.d t0, (t1)20# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]21# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}22lr.d t0, (t1)23# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)24# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]25# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}26lr.d.aq t1, (t2)27# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)28# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]29# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}30lr.d.rl t2, (t3)31# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)32# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]33# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}34lr.d.aqrl t3, (t4)35 36# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)37# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]38# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}39sc.d t6, t5, (t4)40# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)41# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]42# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}43sc.d.aq t5, t4, (t3)44# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)45# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]46# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}47sc.d.rl t4, t3, (t2)48# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)49# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]50# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}51sc.d.aqrl t3, t2, (t1)52