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1# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfh -M no-aliases -show-encoding \2# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s3# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfh < %s \4# RUN: | llvm-objdump --mattr=+zfh -M no-aliases -d -r - \5# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s6#7# RUN: not llvm-mc -triple riscv32 -mattr=+zfh < %s 2>&1 \8# RUN: | FileCheck -check-prefix=CHECK-RV32 %s9 10# CHECK-ASM-AND-OBJ: fcvt.l.h a0, ft0, dyn11# CHECK-ASM: encoding: [0x53,0x75,0x20,0xc4]12# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}13fcvt.l.h a0, ft0, dyn14# CHECK-ASM-AND-OBJ: fcvt.lu.h a1, ft1, dyn15# CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc4]16# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}17fcvt.lu.h a1, ft1, dyn18# CHECK-ASM-AND-OBJ: fcvt.h.l ft2, a2, dyn19# CHECK-ASM: encoding: [0x53,0x71,0x26,0xd4]20# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}21fcvt.h.l ft2, a2, dyn22# CHECK-ASM-AND-OBJ: fcvt.h.lu ft3, a3, dyn23# CHECK-ASM: encoding: [0xd3,0xf1,0x36,0xd4]24# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}25fcvt.h.lu ft3, a3, dyn26 27# Rounding modes28# CHECK-ASM-AND-OBJ: fcvt.l.h a4, ft4, rne29# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}30fcvt.l.h a4, ft4, rne31# CHECK-ASM-AND-OBJ: fcvt.lu.h a5, ft5, rtz32# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}33fcvt.lu.h a5, ft5, rtz34# CHECK-ASM-AND-OBJ: fcvt.h.l ft6, a6, rdn35# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}36fcvt.h.l ft6, a6, rdn37# CHECK-ASM-AND-OBJ: fcvt.h.lu ft7, a7, rup38# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}39fcvt.h.lu ft7, a7, rup40