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1# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -M no-aliases -show-encoding \2# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s3# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zhinx %s \4# RUN: | llvm-objdump --mattr=+zhinx -M no-aliases -d -r - \5# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s6#7# RUN: not llvm-mc -triple riscv32 -mattr=+zhinx %s 2>&1 \8# RUN: | FileCheck -check-prefix=CHECK-RV32 %s9 10# CHECK-ASM-AND-OBJ: fcvt.l.h a0, t0, dyn11# CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc4]12# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}13fcvt.l.h a0, t0, dyn14# CHECK-ASM-AND-OBJ: fcvt.lu.h a1, t1, dyn15# CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc4]16# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}17fcvt.lu.h a1, t1, dyn18# CHECK-ASM-AND-OBJ: fcvt.h.l t2, a2, dyn19# CHECK-ASM: encoding: [0xd3,0x73,0x26,0xd4]20# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}21fcvt.h.l t2, a2, dyn22# CHECK-ASM-AND-OBJ: fcvt.h.lu t3, a3, dyn23# CHECK-ASM: encoding: [0x53,0xfe,0x36,0xd4]24# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}25fcvt.h.lu t3, a3, dyn26 27# Rounding modes28# CHECK-ASM-AND-OBJ: fcvt.l.h a4, t4, rne29# CHECK-ASM: encoding: [0x53,0x87,0x2e,0xc4]30# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}31fcvt.l.h a4, t4, rne32# CHECK-ASM-AND-OBJ: fcvt.lu.h a5, t5, rtz33# CHECK-ASM: encoding: [0xd3,0x17,0x3f,0xc4]34# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}35fcvt.lu.h a5, t5, rtz36# CHECK-ASM-AND-OBJ: fcvt.h.l t6, a6, rdn37# CHECK-ASM: encoding: [0xd3,0x2f,0x28,0xd4]38# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}39fcvt.h.l t6, a6, rdn40# CHECK-ASM-AND-OBJ: fcvt.h.lu s7, a7, rup41# CHECK-ASM: encoding: [0xd3,0xbb,0x38,0xd4]42# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}43fcvt.h.lu s7, a7, rup44