164 lines · plain
1# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -M no-aliases \2# RUN: | FileCheck -check-prefix=CHECK-INST %s3# RUN: llvm-mc %s -triple=riscv32 -mattr=+f \4# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s5# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -M no-aliases \6# RUN: | FileCheck -check-prefix=CHECK-INST %s7# RUN: llvm-mc %s -triple=riscv64 -mattr=+f \8# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s9# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \10# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+f -M no-aliases - \11# RUN: | FileCheck -check-prefix=CHECK-INST %s12# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \13# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+f - \14# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s15# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \16# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+f -M no-aliases - \17# RUN: | FileCheck -check-prefix=CHECK-INST %s18# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \19# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+f - \20# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s21 22##===----------------------------------------------------------------------===##23## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)24##===----------------------------------------------------------------------===##25 26# CHECK-INST: flw ft0, 0(a0)27# CHECK-ALIAS: flw ft0, 0(a0)28flw f0, (a0)29# CHECK-INST: fsw ft0, 0(a0)30# CHECK-ALIAS: fsw ft0, 0(a0)31fsw f0, (a0)32 33# CHECK-INST: fsgnj.s ft0, ft1, ft134# CHECK-ALIAS: fmv.s ft0, ft135fmv.s f0, f136# CHECK-INST: fsgnjx.s ft1, ft2, ft237# CHECK-ALIAS: fabs.s ft1, ft238fabs.s f1, f239# CHECK-INST: fsgnjn.s ft2, ft3, ft340# CHECK-ALIAS: fneg.s ft2, ft341fneg.s f2, f342 43# CHECK-INST: flt.s tp, ft6, ft544# CHECK-ALIAS: flt.s tp, ft6, ft545fgt.s x4, f5, f646# CHECK-INST: fle.s t2, fs1, fs047# CHECK-ALIAS: fle.s t2, fs1, fs048fge.s x7, f8, f949 50# The following instructions actually alias instructions from the base ISA.51# However, it only makes sense to support them when the F or Zfinx extension is52# enabled.53# CHECK-INST: csrrs t0, fcsr, zero54# CHECK-ALIAS: frcsr t055frcsr x556# CHECK-INST: csrrw t1, fcsr, t257# CHECK-ALIAS: fscsr t1, t258fscsr x6, x759# CHECK-INST: csrrw zero, fcsr, t360# CHECK-ALIAS: fscsr t361fscsr x2862 63# These are obsolete aliases of frcsr/fscsr. They are accepted by the assembler64# but the disassembler should always print them as the equivalent, new aliases.65# CHECK-INST: csrrs t4, fcsr, zero66# CHECK-ALIAS: frcsr t467frsr x2968# CHECK-INST: csrrw t5, fcsr, t669# CHECK-ALIAS: fscsr t5, t670fssr x30, x3171# CHECK-INST: csrrw zero, fcsr, s072# CHECK-ALIAS: fscsr s073fssr x874 75# CHECK-INST: csrrs t4, frm, zero76# CHECK-ALIAS: frrm t477frrm x2978# CHECK-INST: csrrw t5, frm, t479# CHECK-ALIAS: fsrm t5, t480fsrm x30, x2981# CHECK-INST: csrrw zero, frm, t682# CHECK-ALIAS: fsrm t683fsrm x3184# CHECK-INST: csrrwi a0, frm, 3185# CHECK-ALIAS: fsrmi a0, 3186fsrmi x10, 0x1f87# CHECK-INST: csrrwi zero, frm, 3088# CHECK-ALIAS: fsrmi 3089fsrmi 0x1e90 91# CHECK-INST: csrrs a1, fflags, zero92# CHECK-ALIAS: frflags a193frflags x1194# CHECK-INST: csrrw a2, fflags, a195# CHECK-ALIAS: fsflags a2, a196fsflags x12, x1197# CHECK-INST: csrrw zero, fflags, a398# CHECK-ALIAS: fsflags a399fsflags x13100# CHECK-INST: csrrwi a4, fflags, 29101# CHECK-ALIAS: fsflagsi a4, 29102fsflagsi x14, 0x1d103# CHECK-INST: csrrwi zero, fflags, 28104# CHECK-ALIAS: fsflagsi 28105fsflagsi 0x1c106 107# CHECK-INST: fmv.x.w a2, fs7108# CHECK-ALIAS: fmv.x.w a2, fs7109fmv.x.s a2, fs7110# CHECK-INST: fmv.w.x ft1, a6111# CHECK-ALIAS: fmv.w.x ft1, a6112fmv.s.x ft1, a6113 114# CHECK-INST: flw ft0, 0(a0)115# CHECK-ALIAS: flw ft0, 0(a0)116flw f0, (x10)117# CHECK-INST: fsw ft0, 0(a0)118# CHECK-ALIAS: fsw ft0, 0(a0)119fsw f0, (x10)120 121##===----------------------------------------------------------------------===##122## Aliases which omit the rounding mode.123##===----------------------------------------------------------------------===##124 125# CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn126# CHECK-ALIAS: fmadd.s fa0, fa1, fa2, fa3{{[[:space:]]}}127fmadd.s f10, f11, f12, f13128# CHECK-INST: fmsub.s fa4, fa5, fa6, fa7, dyn129# CHECK-ALIAS: fmsub.s fa4, fa5, fa6, fa7{{[[:space:]]}}130fmsub.s f14, f15, f16, f17131# CHECK-INST: fnmsub.s fs2, fs3, fs4, fs5, dyn132# CHECK-ALIAS: fnmsub.s fs2, fs3, fs4, fs5{{[[:space:]]}}133fnmsub.s f18, f19, f20, f21134# CHECK-INST: fnmadd.s fs6, fs7, fs8, fs9, dyn135# CHECK-ALIAS: fnmadd.s fs6, fs7, fs8, fs9{{[[:space:]]}}136fnmadd.s f22, f23, f24, f25137# CHECK-INST: fadd.s fs10, fs11, ft8, dyn138# CHECK-ALIAS: fadd.s fs10, fs11, ft8{{[[:space:]]}}139fadd.s f26, f27, f28140# CHECK-INST: fsub.s ft9, ft10, ft11, dyn141# CHECK-ALIAS: fsub.s ft9, ft10, ft11{{[[:space:]]}}142fsub.s f29, f30, f31143# CHECK-INST: fmul.s ft0, ft1, ft2, dyn144# CHECK-ALIAS: fmul.s ft0, ft1, ft2{{[[:space:]]}}145fmul.s ft0, ft1, ft2146# CHECK-INST: fdiv.s ft3, ft4, ft5, dyn147# CHECK-ALIAS: fdiv.s ft3, ft4, ft5{{[[:space:]]}}148fdiv.s ft3, ft4, ft5149# CHECK-INST: fsqrt.s ft6, ft7, dyn150# CHECK-ALIAS: fsqrt.s ft6, ft7{{[[:space:]]}}151fsqrt.s ft6, ft7152# CHECK-INST: fcvt.w.s a0, fs5, dyn153# CHECK-ALIAS: fcvt.w.s a0, fs5{{[[:space:]]}}154fcvt.w.s a0, fs5155# CHECK-INST: fcvt.wu.s a1, fs6, dyn156# CHECK-ALIAS: fcvt.wu.s a1, fs6{{[[:space:]]}}157fcvt.wu.s a1, fs6158# CHECK-INST: fcvt.s.w ft11, a4, dyn159# CHECK-ALIAS: fcvt.s.w ft11, a4{{[[:space:]]}}160fcvt.s.w ft11, a4161# CHECK-INST: fcvt.s.wu ft0, a5, dyn162# CHECK-ALIAS: fcvt.s.wu ft0, a5{{[[:space:]]}}163fcvt.s.wu ft0, a5164