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1# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcibi %s \2# RUN: | FileCheck -check-prefix=ASM %s3# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcibi %s \4# RUN: -filetype=obj -o - \5# RUN: | llvm-objdump -dr --mattr=+experimental-xqcibi - \6# RUN: | FileCheck -check-prefix=OBJ %s7 8## This test checks that we emit the right relocations for Xqcibi9## relative branches. These can be resolved within the same section10## (when relaxations are disabled) but otherwise require a relocation.11## The QC.E.B<op>I instructions also require a vendor relocation.12 13# This is required so that the conditional branches requiring relocations14# are not converted into inverted branches with long jumps by the assembler.15.option exact16 17# ASM-LABEL: this_section:18# OBJ-LABEL: <this_section>:19this_section:20 21# ASM: qc.bnei t1, 10, undef22# OBJ: qc.bnei t1, 0xa, 0x0 <this_section>23# OBJ-NEXT: R_RISCV_BRANCH undef{{$}}24qc.bnei t1, 10, undef25 26# ASM: qc.e.bgeui s0, 20, undef27# OBJ-NEXT: qc.e.bgeui s0, 0x14, 0x4 <this_section+0x4>28# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}29# OBJ-NEXT: R_RISCV_CUSTOM193 undef{{$}}30qc.e.bgeui s0, 20, undef31 32 33# ASM: qc.bnei t2, 11, same_section34# OBJ-NEXT: qc.bnei t2, 0xb, 0x28 <same_section>35qc.bnei t2, 11, same_section36 37# ASM: qc.e.bgeui s1, 21, same_section38# OBJ-NEXT: qc.e.bgeui s1, 0x15, 0x28 <same_section>39qc.e.bgeui s1, 21, same_section40 41 42# ASM: qc.bnei t2, 12, same_section_extern43# OBJ-NEXT: qc.bnei t2, 0xc, 0x14 <this_section+0x14>44# OBJ-NEXT: R_RISCV_BRANCH same_section_extern{{$}}45qc.bnei t2, 12, same_section_extern46 47# ASM: qc.e.bgeui s1, 22, same_section_extern48# OBJ-NEXT: qc.e.bgeui s1, 0x16, 0x18 <this_section+0x18>49# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}50# OBJ-NEXT: R_RISCV_CUSTOM193 same_section_extern{{$}}51qc.e.bgeui s1, 22, same_section_extern52 53 54# ASM: qc.bnei t3, 13, other_section55# OBJ-NEXT: qc.bnei t3, 0xd, 0x1e <this_section+0x1e>56# OBJ-NEXT: R_RISCV_BRANCH other_section{{$}}57qc.bnei t3, 13, other_section58 59# ASM: qc.e.bgeui s2, 23, other_section60# OBJ-NEXT: qc.e.bgeui s2, 0x17, 0x22 <this_section+0x22>61# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}62# OBJ-NEXT: R_RISCV_CUSTOM193 other_section{{$}}63qc.e.bgeui s2, 23, other_section64 65 66# ASM-LABEL: same_section:67# OBJ-LABEL: <same_section>:68same_section:69 nop70 71# ASM-LABEL: same_section_extern:72# OBJ-LABEL: <same_section_extern>:73 .global same_section_extern74same_section_extern:75 nop76 77.option relax78 79# ASM: qc.bnei t3, 14, same_section80# OBJ: qc.bnei t3, 0xe, 0x28 <same_section>81qc.bnei t3, 14, same_section82 83# ASM: qc.e.bgeui s2, 24, same_section84# OBJ-NEXT: qc.e.bgeui s2, 0x18, 0x28 <same_section>85qc.e.bgeui s2, 24, same_section86 87## Enable compression/relaxation to check how symbols are handled.88.option noexact89 90# ASM: qc.bnei t1, 10, undef91# OBJ: qc.beqi t1, 0xa, 0x42 <same_section_extern+0x16>92# OBJ-NEXT: j 0x3e <same_section_extern+0x12>93# OBJ-NEXT: R_RISCV_JAL undef{{$}}94qc.bnei t1, 10, undef95 96# ASM: qc.e.bgeui s0, 40, undef97# OBJ-NEXT: qc.e.bltui s0, 0x28, 0x4c <same_section_extern+0x20>98# OBJ-NEXT: j 0x48 <same_section_extern+0x1c>99# OBJ-NEXT: R_RISCV_JAL undef{{$}}100qc.e.bgeui s0, 40, undef101 102.section .text.second, "ax", @progbits103 104# ASM-LABEL: other_section:105# OBJ-LABEL: <other_section>:106other_section:107 nop108