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1# Xqcicsr - Qualcomm uC CSR Extension2# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicsr < %s 2>&1 \3# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s4# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicsr < %s 2>&1 \5# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s6 7# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)8# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction9qc.csrrwr x10, x5, x010 11# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction12qc.csrrwr x10, x513 14# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)15qc.csrrwr x10, x5, x2016 17 18# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)19# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction20qc.csrrwri x20, 31, x021 22# CHECK-PLUS: :[[@LINE+1]]:17: error: immediate must be an integer in the range [0, 31]23qc.csrrwri x20, 45, x1224 25# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction26qc.csrrwri x20, 2327 28# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)29qc.csrrwri x30, 31, x1230