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1# RUN: llvm-mc -filetype=obj -triple x86_64 --x86-align-branch-boundary=32 --x86-align-branch=jmp %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s2 3 # Exercise cases where we're enabling interrupts with one instruction delay4 # and thus can't add a nop in between without changing behavior.5 6 .text7 8 # CHECK: 1e: sti9 # CHECK: 1f: jmp10 .p2align 511 .rept 3012 int313 .endr14 sti15 jmp baz16 17 # CHECK: 5c: movq %rax, %ss18 # CHECK: 5f: jmp19 .p2align 520 .rept 2821 int322 .endr23 movq %rax, %ss24 jmp baz25 26 # CHECK: 9d: movl %esi, %ss27 # CHECK: 9f: jmp28 .p2align 529 .rept 2930 int331 .endr32 movl %esi, %ss33 jmp baz34 35 # movw and movl are interchangeable since we're only using the low 16 bits.36 # Both are generated as "MOV Sreg,r/m16**" (8E /r), but disassembled as movl37 # CHECK: dd: movl %esi, %ss38 # CHECK: df: jmp39 .p2align 540 .rept 2941 int342 .endr43 movw %si, %ss44 jmp baz45 46 # CHECK: 11b: movw (%esi), %ss47 # CHECK: 11e: jmp48 .p2align 549 .rept 2750 int351 .endr52 movw (%esi), %ss53 jmp baz54 55 # CHECK: 15b: movw (%rsi), %ss56 # CHECK: 15d: jmp57 .p2align 558 .rept 2759 int360 .endr61 movw (%rsi), %ss62 jmp baz63 64 65 int366 .section ".text.other"67bar:68 retq69